AT89LP52 Atmel Corporation, AT89LP52 Datasheet - Page 19

• Manufacturer Part Number: AT89LP52
• Manufacturer: Atmel Corporation

Specifications of AT89LP52

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

3709D–MICRO–12/11
Figure 3-10. External Data Memory 16-bit Linear Address Mode
Figure 3-11
using an 8-bit paged address. Port 0 serves as a multiplexed address/data bus to the RAM. The
ALE strobe is used to latch the address byte into an external register so that Port 0 can be freed
for data input/output. The Port 2 I/O lines (or other ports) can provide control lines to page the
memory; however, this operation is not handled automatically by hardware. The software appli-
cation must change the Port 2 register when appropriate to access different pages. The
MOVX @Ri instructions use Paged Address mode.
Figure 3-11. External Data Memory 8-bit Paged Address Mode
Note that prior to using the external memory interface, WR (P3.6) and RD (P3.7) must be config-
ured as outputs. See
automatically to push-pull output mode when outputting address or data and P0 is automatically
tristated when inputting data regardless of the port configuration. The Port 0 configuration will
determine the idle state of Port 0 when not accessing the external memory.
Figure 3-12
respectively. The address on P0 and P2 is stable at the falling edge of ALE. The idle state of
ALE is controlled by DISALE (AUXR.0). When DISALE = 0 the ALE toggles at a constant rate
when not accessing external memory. When DISALE = 1 the ALE is weakly pulled high. DISALE
must be one in order to use P4.4 as a general-purpose I/O. The WS bits in AUXR can extended
the RD and WR strobes by 1, 2 or 3 cycles as shown in Figures 3-16, 3-17 and 3-18. If a longer
strobe is required, the application can scale the system clock with the clock divider to meet the
requirements (See
and
shows a hardware configuration for accessing 256-byte blocks of external RAM
Figure 3-13
Section 6.4 on page
Section 10.1 “Port Configuration” on page
P1
P1
RD
WR
RD
WR
show examples of external data memory write and read cycles,
AT89LP
AT89LP
P3
P3
P2
ALE
ALE
P0
P2
P0
31).
I/O
LATCH
LATCH
PAGE
BITS
DATA
DATA
EXTERNAL
EXTERNAL
MEMORY
WE
MEMORY
WE
ADDR
ADDR
DATA
DATA
41. P0 and P2 are configured
OE
OE
AT89LP51/52
19