AT89LP52 Atmel Corporation, AT89LP52 Datasheet - Page 31

• Manufacturer Part Number: AT89LP52
• Manufacturer: Atmel Corporation

Specifications of AT89LP52

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

6.4
Table 6-2.
Note:
3709D–MICRO–12/11
TPS[3-0]
CDV[2-0]
Symbol
CLKREG = 8FH
Not Bit Addressable
Bit
System Clock Divider
The reset value of CLKREG is 0000000B in Fast mode and 01010010B in Compatibility mode.
Function
Timer Prescaler. The Timer Prescaler selects the time base for Timer 0, Timer 1, Timer 2 and the Watchdog Timer. The
prescaler is implemented as a 4-bit binary down counter. When the counter reaches zero it is reloaded with the value
stored in the TPS bits to give a division ratio between 1 and 16. By default the timers will count every clock cycle in Fast
mode (TPS = 0000B) and every six cycles in Compatibility mode (TPS = 0101B).
System Clock Division. Determines the frequency of the system clock relative to the oscillator clock source.
CDIV2
0
0
0
0
1
1
1
1
CLKREG
TPS3
7
– Clock Control Register
CDIV1
0
0
1
1
0
0
1
1
The CDV
source by powers of 2. The clock divider provides users with a greater frequency range when
using the Internal Oscillator. For example, to achieve a 230.4 kHz system frequency when using
the RC oscillator, CDV
be used to reduce power consumption by decreasing the operational frequency during non-criti-
cal periods. The resulting system frequency is given by the following equation:
where f
for the CPU and all peripherals. The value of CDV may be changed at any time without interrupt-
ing normal execution. Changes to CDV are synchronized such that the system clock will not
pass through intermediate frequencies. When CDV is updated, the new frequency will take
affect within a maximum period of 32 x t
In Compatibility mode the divider defaults to divide-by-2 and and in Fast mode it defaults to no
division.
TPS2
6
OSC
CDIV0
0
1
0
1
0
1
0
1
2-0
is the frequency of the selected clock source. The clock divider will prescale the clock
bits in CLKREG allow the system clock to be divided down from the selected clock
TPS1
5
System Clock Frequency
f
f
f
f
f
f
Reserved
Reserved
OSC
OSC
OSC
OSC
OSC
OSC
/1
/2
/4
/8
/16
/32
2-0
should be set to 011B for divide-by-8 operation. The divider can also
TPS0
4
OSC
CDV2
f
SYS
.
3
=
------------ -
2
f
OSC
CDV
CDV1
2
Reset Value = 0?0? 00?0B
CDV0
1
AT89LP51/52
—
0
31