AT89LP52 Atmel Corporation, AT89LP52 Datasheet - Page 78

• Manufacturer Part Number: AT89LP52
• Manufacturer: Atmel Corporation

Specifications of AT89LP52

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

78
AT89LP51/52
Table 16-1.
Notes:
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
Branching
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
JZ rel
JNZ rel
SJMP rel
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
JMP @A+DPTR
JMP @A+PC
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
CJNE A, @R0, rel
CJNE A, @R1, rel
DJNZ Rn, rel
DJNZ direct, rel
NOP
1. A clock cycle is one period of the output of the system clock divider. For Fast mode the divider
2. This escaped instruction is an extension to the instruction set.
3. This is the minimum time for MOVX with no wait states. In Compatibility mode an additional 24
defaults to 1, so the clock cycle equals the oscillator period. For Compatibility mode the divider
defaults to 2, so the clock cycle is twice the oscillator period, or conversely the clock count is
half the number of oscillator periods.
clocks are added for the wait state. In Fast mode, 1 clock is added for each wait state (0–3).
(2)
Instruction Execution Times and Exceptions
(2)
(2)
Bytes
2
2
2
2
2
2
3
3
3
2
2
2
2
3
1
1
2
3
1
2
3
3
3
3
3
3
2
3
1
Compatibility
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
18
18
12
12
6
6
(1)
Clock Cycles
(Continued)
Fast
2
2
2
2
3
3
4
4
4
3
3
3
3
4
4
4
3
4
2
3
4
4
4
4
4
3
4
1
4
3709D–MICRO–12/11
11,31,51,71,91,
01,21,41,61,81,
Hex Code
A1,C1,E1
B1,D1,F1
D8-DF
B8-BF
B6-B7
A5 B6
A5 B7
A5 73
A0
A2
B5
B4
D5
72
92
40
50
20
30
10
60
70
80
12
22
32
02
73
00