AT89LP52 Atmel Corporation, AT89LP52 Datasheet - Page 36

• Manufacturer Part Number: AT89LP52
• Manufacturer: Atmel Corporation

Specifications of AT89LP52

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

8.2.1
8.2.2
36
AT89LP51/52
Interrupt Recovery from Power-down
Reset Recovery from Power-down
Two external interrupt sources may be configured to terminate Power-down mode: external
interrupts INT0 (P3.2) and INT1 (P3.3). To wake up by external interrupt INT0 or INT1, that inter-
rupt must be enabled by setting EX0 or EX1 in IE and must be configured for level-sensitive
operation by clearing IT0 or IT1.
When terminating Power-down by an interrupt, two different wake-up modes are available.
When PWDEX in PCON is one, the wake-up period is internally timed as shown in
the falling edge on the interrupt pin, Power-down is exited, the oscillator is restarted, and an
internal timer begins counting. The internal clock will not be allowed to propagate to the CPU
until after the timer has timed out. After the time-out period the interrupt service routine will
begin. The time-out period is controlled by the Start-up Timer Fuses (see
The interrupt pin need not remain low for the entire time-out period.
Figure 8-1.
When PWDEX = “0”, the wake-up period is controlled externally by the interrupt. Again, at the
falling edge on the interrupt pin, power-down is exited and the oscillator is restarted. However,
the internal clock will not propagate until the rising edge of the interrupt pin as shown in
2. The interrupt pin should be held low long enough for the selected clock source to stabilize.
After the rising edge on the pin the interrupt service routine will be executed.
Figure 8-2.
The wake-up from Power-down through an external reset is similar to the interrupt with
PWDEX = “1”. At the rising edge of RST, Power-down is exited, the oscillator is restarted, and
an internal timer begins counting as shown in
propagate to the CPU until after the timer has timed out. The time-out period is controlled by the
Start-up Timer Fuses. (See
clock cycle internal reset is generated when the internal clock restarts. Otherwise, the device will
remain in reset until RST is brought low.
Internal
Internal
XTAL1
XTAL1
Clock
PWD
Clock
INT1
PWD
INT1
Interrupt Recovery from Power-down (PWDEX = 1)
Interrupt Recovery from Power-down (PWDEX = 0)
Table 7-1 on page
Figure
33). If RST returns low before the time-out, a two
t SUT
8-3. The internal clock will not be allowed to
Table 7-1 on page
3709D–MICRO–12/11
Figure
Figure 8-
8-1. At
33).