AT89LP52 Atmel Corporation, AT89LP52 Datasheet - Page 82

• Manufacturer Part Number: AT89LP52
• Manufacturer: Atmel Corporation

Specifications of AT89LP52

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

17.3
Figure 17-4. Command Sequence Flow Chart
82
Command Format
AT89LP51/52
Programming commands consist of an opcode byte, two address bytes, and one or 64 data
bytes.
A sample command packet is shown in
select. Command bytes are issued serially on MOSI. Data output bytes are received serially on
MISO. The command is not complete until all bytes have been transfered, including any don’t
care bytes.
Page oriented instructions always include a full 16-bit address. The higher order bits select the
page and the lower order bits select the byte within that page. The AT89LP51/52 allocates 6 bits
for byte address, 1 bit for low/high half page selection and 9 bits for page address. The half page
to be accessed is always fixed by the page address and half select as transmitted. The byte
address specifies the starting address for the first data byte. After each data byte has been
transmitted, the byte address is incremented to point to the next data byte. This allows a page
command to linearly sweep the bytes within a page. If the byte address is incremented past the
last byte in the half page, the byte address will roll over to the first byte in the same half page.
While loading bytes into the page buffer, overwriting previously loaded bytes will result in data
corruption.
For a summary of available commands, see
Figure 17-4 on page 82
Input Address
Input Address
Input Opcode
Input/Output
Byte Mode or
Count == 64
High Byte
Low Byte
yes
Data
shows a simplified flow chart of a command sequence.
no
Figure 17-5 on page
Table 17-2 on page
Address +1
83. The packet does not use a chip
84.
3709D–MICRO–12/11