AT89LP52 Atmel Corporation, AT89LP52 Datasheet - Page 64

• Manufacturer Part Number: AT89LP52
• Manufacturer: Atmel Corporation

Specifications of AT89LP52

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

Figure 14-1. Mode 0 Waveforms (Two-Wire)
Figure 14-2. UART Mode 0 TWI Emulation (SMOD1 = 1)
64
Write to SBUF
(SDA) RXD
(SCL) TXD
AT89LP51/52
SMOD1 = 0
SM2 = 0
SMOD1 = 1
SM2 = 0
SMOD1 = 0
SM2 = 1
SMOD1 = 1
SM2 = 1
SM2
P3.0
TI
RXD (RX)
RXD (RX)
RXD (RX)
RXD (RX)
RXD (TX)
RXD (TX)
RXD (TX)
RXD (TX)
state of the clock when not currently transmitting/receiving. The SMOD1 bit determines if the
output data is stable for both edges of the clock, or just one.
Table 14-5.
In Two-Wire configuration Mode 0 may be used as a hardware accelerator for software emula-
tion of serial interfaces such as a half-duplex Serial Peripheral Interface (SPI) master in mode
(0,0) or (1,1) or a Two-Wire Interface (TWI) in master mode. An example of Mode 0 emulating a
TWI master device is shown in
are handled in software while the byte transmission is done in hardware. Falling/rising edges on
TXD are created by setting/clearing SM2. Rising/falling edges on RXD are forced by set-
ting/clearing the P3.0 register bit. SM2 and P3.0 must be 1 while the byte is being transferred.
TXD
TXD
TXD
TXD
SM2
0
0
1
1
0
SMOD1
1
Mode 0 Clock and Data Modes
0
1
0
1
0
0
0
0
0
0
0
0
2
1
1
1
1
1
1
Clock Idle
1
1
High
High
Low
Low
3
2
2
Figure
2
2
2
2
2
2
4
3
3
14-2. In this example, the start, stop, and acknowledge
3
3
3
3
3
3
Negative edge of clock
Negative edge of clock
While clock is high
While clock is low
Data Changes
5
4
4
4
4
4
4
4
4
6
5
5
5
5
5
5
Sample ACK
5
5
7
6
6
6
6
6
6
6
6
ACK
Negative edge of clock
Positive edge of clock
Positive edge of clock
Positive edge of clock
7
7
7
7
7
7
7
7
Data Sampled
3709D–MICRO–12/11