AT89LP52 Atmel Corporation, AT89LP52 Datasheet - Page 8

• Manufacturer Part Number: AT89LP52
• Manufacturer: Atmel Corporation

Specifications of AT89LP52

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

2.2.2
2.3
8
Comparison to AT89S51/52
AT89LP51/52
Software Options
Table 2-1.
Table 2-2
level. These can be changed by the application software but are set to their default values upon
any reset. Most peripherals also have multipe configuration bits that are not listed here.
Table 2-2.
The AT89LP51/52 is part of a family of devices with enhanced features that are fully binary com-
patible with the 8051 instruction set. The AT89LP51/52 has two modes of operations,
Compatibility mode and Fast mode. In Compatibility mode the instruction timing, peripheral
behavior, SFR addresses, bit assignments and pin functions are identical to Atmel's existing
AT89S51/52 product. Additional enhancements are transparent to the user and can be used if
desired. Fast mode allows greater performance, but with some differences in behavior. The
major enhancements from the AT89S51/52 are outlined in the following paragraphs and may be
useful to users migrating to the AT89LP51/52 from older devices. A summary of the differences
between Compatibility and Fast modes is given in
tion note “Migrating from AT89S52 to AT89LP52.”
Fuse Name
Clock Source
Start-up Time
Compatibility Mode
In-System Programming Enable
User Signature Programming
Tristate Ports
In-Application Programming
R1 Enable
Bit(s)
PxM0
PxM1
CDV
TPS
DISALE
EXRAM
WS
DMEN
IAP
1-0
3-0
2-0
lists some important software configuration bits that affect operation at the system
SFR Location
PMOD
CLKREG.3-1
CLKREG.7-4
AUXR.0
AUXR.1
AUXR.3-2
MEMCON.3
MEMCON.7
User Configuration Fuses
Important Software Configuration Bits
Description
Selects between the High Speed Crystal Oscillator, Low Speed
Crystal Oscillator, External Clock or Internal RC Oscillator for the
source of the system clock.
Selects time-out delay for the POR/BOD/PWD wake-up period.
Configures the CPU in 12-clock Compatibility mode or single-cycle
Fast mode
Enables or disables In-System Programming.
Enables or disables programming of User Signature array.
Configures the default port state as input-only mode (tristated) or
quasi-bidirectional mode (weakly pulled high).
Enables or disables In-Application (self) Programming
Description
Configures the I/O mode of all pins of Port x to be nput-only, quasi-
bidirectional, push-pull output or open-drain. The default state is
controlled by the Default Port State fuse above
Selects the division ratio between the oscillator and the system clock
Selects the division ratio between the system clock and the timers
Enables/disables toggling of ALE
Enables/disables access to on-chip memories that are mapped to the
external data memory address space
Selects the number of wait states when accessing external data
memory
Enables/disables access to the on-chip flash data memory
Enbles/disables the self programming feature when the fuse allows
Table 2-3 on page
10. See also the Applica-
3709D–MICRO–12/11