AT89LP52 Atmel Corporation, AT89LP52 Datasheet - Page 23

• Manufacturer Part Number: AT89LP52
• Manufacturer: Atmel Corporation

Specifications of AT89LP52

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

3.4
3709D–MICRO–12/11
In-Application Programming (IAP)
The AT89LP51/52 supports In-Application Programming (IAP), allowing the program memory to
be modified during execution. IAP can be used to modify the user application on the fly or to use
program memory for nonvolatile data storage. The same page structure write protocol for
FDATA also applies to IAP (See
always placed in idle while modifying the program memory. When the write completes, the CPU
will continue executing with the instruction after the MOVX @DPTR,A instruction that started the
write.
To enable access to the program memory, the IAP bit (MEMCON.7) must be set to one and the
IAP User Fuse must be enabled. The IAP User Fuse can disable all IAP operations. When this
fuse is disabled, the IAP bit will be forced to 0. While IAP is enabled, all MOVX @DPTR instruc-
tions will access the CODE space instead of EDATA/FDATA/XDATA. IAP also allows
reprogramming of the User Signature Array when SIGEN = 1. The IAP access settings are sum-
marized in
Table 3-4.
Table 3-5.
Note:
IAP
IAP
0
0
0
0
1
1
0
0
0
0
1
1
When In-Application programming is not required, it is recommended that the IAP User Fuse be
disabled.
Table 3-4
SIGEN
SIGEN
IAP Access Settings for AT89LP52
0
0
1
1
0
1
IAP Access Settings for AT89LP51
0
0
1
1
0
1
and
DMEN
DMEN
X
X
X
X
0
1
0
1
0
1
0
1
Table
3-5.
Section 3.3.2.1 “Write Protocol” on page
XDATA (0000–FFFFH)
XDATA (0100–FFFFH)
XDATA (0000–FFFFH)
XDATA (0100–FFFFH)
XDATA (2000–FFFFH)
XDATA (2000–FFFFH)
XDATA (0000–FFFFH)
XDATA (0100–FFFFH)
XDATA (0000–FFFFH)
XDATA (0100–FFFFH)
XDATA (1000–FFFFH)
XDATA (1000–FFFFH)
FDATA (0000–00FFH)
FDATA (0000–00FFH)
CODE (0000–1FFFH)
FDATA (0000–00FFH)
FDATA (0000–00FFH)
CODE (0000–0FFFH)
SIG (0000–01FFH)
SIG (0000–01FFH)
MOVX @DPTR
MOVX @DPTR
XCODE (2000–FFFFH)
XCODE (2000–FFFFH)
XCODE (2000–FFFFH)
XCODE (1000–FFFFH)
XCODE (1000–FFFFH)
XCODE (1000–FFFFH)
CODE (0000–1FFFH)
CODE (0000–1FFFH)
CODE (0000–1FFFH)
CODE (0000–0FFFH)
CODE (0000–0FFFH)
CODE (0000–0FFFH)
AT89LP51/52
SIG (0000–01FFH)
SIG (0000–01FFH)
SIG (0000–01FFH)
SIG (0000–01FFH)
SIG (0000–01FFH)
SIG (0000–01FFH)
MOVC @DPTR
MOVC @DPTR
16). The CPU is
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