AT89LP52 Atmel Corporation, AT89LP52 Datasheet - Page 87

• Manufacturer Part Number: AT89LP52
• Manufacturer: Atmel Corporation

Specifications of AT89LP52

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

Table 17-5.
Notes:
17.8
17.9
17.9.1
3709D–MICRO–12/11
Address
07H
08H
09H
1. The default state for Tristate Ports is 00h. All other fuses default to FFh.
2. Changes to these fuses will only take effect after a device POR.
3. Changes to these fuses will only take effect after the ISP session terminates by bringing RST inactive.
User Signature
Programming Interface Timing
Power-up Sequence
Fuse Name
Tristate Ports
In-Application Programming
R1 Enable
User Configuration Fuse Definitions
The User Signature Array contains 256 bytes of non-volatile memory in two 128-byte pages. The
User Signature is available for serial numbers, firmware revision information, date codes or other
user parameters. The User Signature Array may only be written by an external device when the
User Signature Programming Fuse is enabled. When the fuse is enabled, Chip Erase will also
erase the first page of the array. When the fuse is disabled, the array is not affected by write or
erase commands. Programming of the Signature Array can also be disabled by the Lock Bits.
However, reading the signature is always allowed and the array should not be used to store
security sensitive information. The User Signature Array may be modified during execution
through the In-Application Programming interface, regardless of the state of the User Signature
Programming fuse or Lock Bits, provided that the IAP Fuse is enabled. Note that the address of
the User Signature Array, as seen by the IAP interface, equals the User Signature address plus
256 (0100H–01FFH instead of 0000H–00FFH).
This section details general system timing sequences and constraints for entering or exiting In-
System Programming as well as parameters related to the Serial Peripheral Interface during
ISP. The general timing parameters for the following waveform figures are listed in section
ing Parameters” on page
Execute this sequence to enter programming mode immediately after power-up. In the RST pin
is disabled or if the ISP Fuse is disabled, this is the only method to enter programming (see
“External Reset” on page
1. Apply power between VDD and GND pins. RST should remain low.
2. Wait at least t
3. Wait at least t
4. Start programming session.
depend on the current settings of the device.
PWRUP
SUT
Description
FFh: I/O Ports start in input-only mode (tristated) after reset
00h: I/O Ports start in quasi-bidirectional mode after reset
FFh: In-Application Programming Disabled
00h: In-Application Programming Enabled
FFh: 5 MΩ resistor on XTAL1 Disabled
00h: 5 MΩ resistor on XTAL1 Enabled
for the internal Power-on Reset to complete. The value of t
. and drive RST high if active-high otherwise keep low.
91.
33).
AT89LP51/52
SUT
will
“Tim-
87