AT89LP52 Atmel Corporation, AT89LP52 Datasheet - Page 48

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AT89LP52

Manufacturer Part Number
AT89LP52
Description
Manufacturer
Atmel Corporation
Datasheet

Specifications of AT89LP52

Flash (kbytes)
8 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
36
Uart
1
Sram (kbytes)
0.25
Eeprom (bytes)
256
Self Program Memory
IAP
Operating Voltage (vcc)
2.4 to 5.5
Timers
3
Isp
SPI
Watchdog
Yes

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11.3
11.4
48
Mode 2 – 8-bit Auto-Reload Timer/Counter
Mode 3 – 8-bit Split Timer
AT89LP51/52
Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown
in
TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 2 operation is the
same for Timer/Counter 0.
Figure 11-3. Timer/Counter 1 Mode 2: 8-bit Auto-Reload
Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in
Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is
shown in
is locked into a timer function (counting clock cycles) and takes over the use of TR1 and TF1
from Timer 1. Thus, TH0 now controls the Timer 1 interrupt. While Timer 0 is in Mode 3, Timer 1
will still obey its settings in TMOD but cannot generate an interrupt.
Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the
AT89LP51/52 can appear to have four Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can
be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still
be used by the serial port as a baud rate generator or in any application not requiring an
interrupt.
Figure 11-4. Timer/Counter 0 Mode 3: Two 8-bit Counters
Figure
OSC
OSC
OSC
Figure
11-3. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of
INT0 Pin
INT0 Pin
GATE0
T1 Pin
÷CDV
GATE1
T0 Pin
Mode 2:
÷CDV
÷CDV
11-4. TL0 uses the Timer 0 control bits: C/T, GATE0, TR0, INT0, and TF0. TH0
÷TPS
TR1
÷TPS
÷TPS
Time-out Period
C/T = 0
C/T = 1
C/T = 0
C/T =1
=
------------------------------------------------- -
System Frequency
Control
Control
Control
(
256 TH0
(8 Bits)
(8 Bits)
(8 Bits)
(8 Bits)
TH1
TL1
)
×
(
TPS
Reload
+
1
TF1
)
3709D–MICRO–12/11
Inter r up t
Inter r up t
Inter r up t

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