AT89LP52 Atmel Corporation, AT89LP52 Datasheet - Page 102

• Manufacturer Part Number: AT89LP52
• Manufacturer: Atmel Corporation

Specifications of AT89LP52

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

18.6
The values shown in this table are valid for T
ating conditions, load capacitance for Port 0, ALE and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.
Parameters refer to
Table 18-4.
Notes:
102
Symbol
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LHLL
AVLL
LLAX
LLIV
LLPL
PLPH
PLIV
PXIX
PXIZ
PXAV
AVIV
PLAZ
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
QVWH
WHQX
RLAZ
WHAX
WHLH
CLCL
External Memory Characteristics
1. Compatibility Mode timing for MOVX also applies to Fast Mode during exeternal execution of MOVX.
2. This assumes 50% clock duty cycle. The half period depends on the clock high value t
3. This assumes 50% clock duty cycle. The half period depends on the clock low value t
4. In some cases parameter t
5. The strobe pulse width may be lengthened by 1, 2 or 3 additional t
6. t
AT89LP51/52
CLCL
Parameter
System Frequency
ALE Pulse Width
Address Valid to ALE Low
Address Hold after ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse WIdth
PSEN Low to Valid Instruction In
Input Instruction Hold after PSEN
Input Instruction Float after PSEN
PSEN to Address Valid
Address to Valid Instruction In
PSEN Low to Address Float
RD Pulse Width
WR Pulse Width
RD Low to Valid Data In
Data Hold after RD
Data Float after RD
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address to RD or WR Low
Data Valid to WR Transition
Data Valid to WR High
Data Hold after WR
RD Low to Address Float
Address Hold after RD or WR High
RD or WR High to ALE High
External Program and Data Memory Characteristics
is the internal system clock period. By default in Compatibility Mode, t
Figure
(5)
(5)
18-14,
(6)
Figure 18-15
LHLL
may have a minimum of 0.5t
A
= -40°C to 85°C and V
and
Figure
0.5t
0.5t
0.5t
1.5t
0.5t
2t
1t
4t
1t
1t
1.5t
0.5t
3t
3t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
Compatibility Mode
Min
18-16.
0
0
0
- 20
- 20
- 20
- 20
- 20
- 10
- 20
- 20
- 20
- 10
- 20
- 10
- 10
- 20
- 20
(2)
(2)
(2)
(3)
(3)
(2)
(3)
(2)
(2)
(2)
CLCL
DD
during Fast mode external execution with DISALE = 0.
1.5t
0.5t
2.5t
4.5t
-1t
1.5t
0.5t
2.5t
CLCL
2t
4t
t
CLCL
= 2.4 to 5.5V, unless otherwise noted. Under oper-
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
Max
24
10
using wait states.
+ 20
(1)
- 20
- 30
- 20
- 30
- 30
- 30
- 30
+ 20
+ 20
- 30
CLCL
(2)
(2)
(2)
(2)
(2)
= 2 t
0.5t
0.5t
0.5t
1.5t
0.5t
1.5t
0.5t
1.5t
0.5t
0.5t
t
CLCL
t
t
t
t
OSC
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCX
Min
CHCX
0
- 10
0
0
- 20
- 20
- 10
- 10
- 20
- 20
- 20
- 10
- 20
- 20
- 20
- 20
- 20
- 20
Fast Mode
(low duty cycle).
(4)
(high duty cycle).
(2)
(3)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(3)
-0.5t
1.5t
0.5t
2.5t
2.5t
2t
2t
t
(1)
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
Max
24
10
+ 20
- 30
- 20
- 30
- 20
- 30
- 30
+ 20
- 30
- 30
3709D–MICRO–12/11
(2)
(2)
(2)
(2)
(2)
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns