AT89LP52 Atmel Corporation, AT89LP52 Datasheet - Page 86

• Manufacturer Part Number: AT89LP52
• Manufacturer: Atmel Corporation

Specifications of AT89LP52

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

Table 17-4.
17.7
Table 17-5.
86
Address
00 – 01h
02 – 03h
04h
05h
06H
Mode
1
2
3
4
User Configuration Fuses
Program Lock Bits (by address)
AT89LP51/52
Fuse Name
Clock Source – CS[0:1]
Start-up Time – SUT[0:1]
Compatibility Mode
ISP Enable
User Signature Programming
Lock Bit Protection Modes
User Configuration Fuse Definitions
00h
FFh
00h
00h
00h
(3)
implements mode 2 and also blocks reads from the code and data memories; however, reads of
the User Signature Array, Atmel Signature Array, and User Configuration Fuses are still allowed.
The Lock Bits will not disable FDATA or IAP programming initiated by the application software.
The AT89LP51/52 includes 10 user fuses for configuration of the device. Each fuse is accessed
at a separate address in the User Fuse Row as listed in
gramming 00h to their locations. Programming FFh to a fuse location will cause that fuse to
maintain its previous state. To set a fuse (set to FFh) the fuse row must be erased and then
reprogrammed using the Fuse Write with Auto-erase command. The default state for all fuses is
FFh except for Tristate Ports, which defaults to 00h.
01h
FFh
FFh
00h
00h
(2)
02h
FFh
FFh
FFh
00h
Description
Selects source for the system clock:
CS1
FFh
FFh
00h
00h
Selects time-out delay for the POR/BOD/PWD wake-up period:
SUT1
00h
00h
FFh
FFh
FFh: CPU functions in 12-clock Compatibility mode
00h: CPU functions is single-cycle Fast mode
FFh: In-System Programming Enabled
00h: In-System Programming Disabled (Enabled at POR only)
FFh: Programming of User Signature Disabled
00h: Programming of User Signature Enabled
Protection Mode
No program lock features
Further programming of the Flash is disabled
Further programming of the Flash is disabled and verify (read) is also disabled
Further programming of the Flash is disabled and verify (read) is also disabled;
External execution above 4K/8K is disabled
CS0
FFh
00h
SUT0
00h
FFh
FFh
FFh
00h
00h
Selected Source
High Speed Crystal Oscillator (XTAL)
Low Speed Crystal Oscillator (XTAL)
External Clock on XTAL1 (XCLK)
Internal Auxiliary Oscillator (IRC)
Selected Time-out
1 ms (XTAL); 16 µs (XCLK/IRC)
2 ms (XTAL); 512 µs (XCLK/IRC)
4 ms (XTAL); 1 ms (XCLK/IRC)
16 ms (XTAL); 4 ms (XCLK/IRC)
Table
17-5. Fuses are cleared by pro-
3709D–MICRO–12/11