AT89LP52-20PU Atmel, AT89LP52-20PU Datasheet - Page 85

• Manufacturer Part Number: AT89LP52-20PU
• Description: IC MCU 8051 8K FLASH SPI 40PDIP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP52-20PU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: Serial
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

17.4
Table 17-3.
17.5
17.6
3709B–MICRO–12/10
Symbol
LOAD
SUCCESS
WRTINH
BUSY
Bit
7. Atmel Signature Bytes:
8. Symbol Key:
Status Register
DATA Polling
Flash Security
Function
Load flag. Cleared low by the load page buffer command and set high by the next memory write. This flag signals that
the page buffer was previously loaded with data by the load page buffer command.
Success flag. Cleared low at the start of a programming cycle and will only be set high if the programming cycle
completes without interruption from the brownout detector.
Write Inhibit flag. Cleared low by the brownout detector (BOD) whenever programming is inhibited due to V
below the minimum required programming voltage. If a BOD episode occurs during programming, the SUCCESS flag
will remain low after the cycle is complete.
Busy flag. Cleared low whenever the memory is busy programming or if write is currently inhibited.
Status
AT89LP51:
AT89LP52:
Address:
–
7
Register
a:
b:
s:
x:
The current state of the memory may be accessed by reading the status register. The status reg-
ister is shown in
The AT89LP51/52 implements DATA polling to indicate the end of a programming cycle. While
the device is busy, any attempted read of the last byte written will return the data byte with the
MSB complemented. Once the programming cycle has completed, the true value will be acces-
sible. During Erase the data is assumed to be FFH and DATA polling will return 7FH. When
writing multiple bytes in a page, the DATA value will be the last data byte loaded before pro-
gramming begins, not the written byte with the highest physical address within the page.
The AT89LP51/52 provides three Lock Bits for Flash Code and Data Memory security. Lock bits
can be left unprogrammed (FFh) or programmed (00h) to obtain the protection levels listed in
Table
programming of all memory spaces, including the User Signature Array and User Configuration
Fuses. User fuses must be programmed before enabling Lock bit mode 2 or 3. Lock bit mode 3
Page Address Bit
Half Page Select Bit
Byte Address Bit
Don’t Care Bit
0000H
1EH
1EH
–
6
17-4. Lock bits can only be erased (set to FFh) by Chip Erase. Lock bit mode 2 disables
0001H
54H
54H
Table
–
5
17-3.
0002H
05H
06H
–
4
LOAD
3
AT89LP51/52 - Preliminary
SUCCESS
2
WRTINH
1
BUSY
0
DD
falling
85