AT32UC3C2512C-A2UR Atmel, AT32UC3C2512C-A2UR Datasheet - Page 31
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AT32UC3C2512C-A2UR
Manufacturer Part Number
AT32UC3C2512C-A2UR
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3C264C-A2UT.pdf
(107 pages)
Specifications of AT32UC3C2512C-A2UR
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, Ethernet, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 11x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Data Bus Width
32 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C2512C-A2UR
Manufacturer:
YAGEO
Quantity:
60 000
4.4.3
4.4.3.1
4.4.3.2
32117BS–AVR-03/11
Processor States
Debug State
Normal RISC State
Figure 4-5.
The AVR32 processor supports several different execution contexts as shown in
Table 4-2.
Mode changes can be made under software control, or can be caused by external interrupts or
exception processing. A mode can be interrupted by a higher priority mode, but never by one
with lower priority. Nested exceptions can be supported with a minimal software overhead.
When running an operating system on the AVR32, user processes will typically execute in the
application mode. The programs executed in this mode are restricted from executing certain
instructions. Furthermore, most system registers together with the upper halfword of the status
register cannot be accessed. Protected memory areas are also not available. All other operating
modes are privileged and are collectively called System Modes. They have full access to all priv-
ileged and unprivileged resources. After a reset, the processor will be in supervisor mode.
The AVR32 can be set in a debug state, which allows implementation of software monitor rou-
tines that can read out and alter system information for use during application development. This
implies that all system and application registers, including the status registers and program
counters, are accessible in debug state. The privileged instructions are also available.
All interrupt levels are by default disabled when debug state is entered, but they can individually
be switched on by the monitor routine by clearing the respective mask bit in the status register.
Bit 15
Priority
1
2
3
4
5
6
N/A
N/A
0
-
T
0
0
-
Mode
Non Maskable Interrupt
Exception
Interrupt 3
Interrupt 2
Interrupt 1
Interrupt 0
Supervisor
Application
The Status Register Low Halfword
Overview of Execution Modes, their Priorities and Privilege Levels.
0
-
0
-
0
-
0
-
0
-
0
-
Security
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Unprivileged
0
-
L
0
Q
0
V
0
Description
Non Maskable high priority interrupt mode
Execute exceptions
General purpose interrupt mode
General purpose interrupt mode
General purpose interrupt mode
General purpose interrupt mode
Runs supervisor calls
Normal program execution mode
N
0
Z
0
Bit 0
C
0
Bit name
Initial value
Carry
Zero
Sign
Overflow
Saturation
Lock
Reserved
Scratch
Reserved
AT32UC3C
Table
4-2.
31