AT32UC3C2512C-A2UR Atmel, AT32UC3C2512C-A2UR Datasheet - Page 78
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AT32UC3C2512C-A2UR
Manufacturer Part Number
AT32UC3C2512C-A2UR
Description
IC MCU AVR32 512K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3C264C-A2UT.pdf
(107 pages)
Specifications of AT32UC3C2512C-A2UR
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, Ethernet, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 11x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Data Bus Width
32 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C2512C-A2UR
Manufacturer:
YAGEO
Quantity:
60 000
Table 7-47.
Note:
7.9.5
32117BS–AVR-03/11
Symbol
SPI6
SPI7
SPI8
SPI9
SPI10
SPI11
SPI12
SPI13
SPI14
SPI15
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
TWIM/TWIS Timing
cess technology. These values are not covered by test limits in production.
SPI Timing, Slave Mode
Parameter
SPCK falling to MISO delay
MOSI setup time before SPCK rises
MOSI hold time after SPCK rises
SPCK rising to MISO delay
MOSI setup time before SPCK falls
MOSI hold time after SPCK falls
NPCS setup time before SPCK rises
NPCS hold time after SPCK falls
NPCS setup time before SPCK falls
NPCS hold time after SPCK rises
Maximum SPI Frequency, Slave Input Mode
The maximum SPI slave input frequency is given by the following formula:
Where
CPOL and NCPHA.
ter for a description of this clock.
Maximum SPI Frequency, Slave Output Mode
The maximum SPI slave output frequency is given by the following formula:
Where
SPI master setup time. Please refer to the SPI masterdatasheet for
mum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the
maximum frequency of the pins.
Figure 7-48
them. Some of these requirements (t
vention. Compliance with the other requirements (t
I2C
, t
HIGH
, and f
SPIn
SPIn
(1)
shows the TWI-bus timing requirements and the compliance of the device with
is the MISO delay, SPI6 or SPI9 depending on CPOL and NCPHA.
is the MOSI setup and hold time, SPI7 + SPI8 or SPI10 + SPI11 depending on
TWCK
) requires user intervention through appropriate programming of the relevant
f
CLKSPI
f
SPCKMAX
is the maximum frequency of the CLK_SPI. Refer to the SPI chap-
f
SPCKMAX
Conditions
capacitor =
r
=
external
and t
40pF
MIN f
=
f
) are met by the device without requiring user inter-
(
MIN f
PINMAX
(
HD-STA
CLKSPI
,
------------------------------------
SPIn
, t
,
SU-STA
Min
----------- -
SPIn
6.5
1.5
1.5
0
0
5
0
0
+
1
1
t
SETUP
)
, t
SU-STO
)
t
SETUP
, t
HD-DAT
AT32UC3C
.
Max
f
PINMAX
29
30
, t
SU-DAT-I2C
t
SETUP
is the maxi-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
, t
is the
LOW-
78