EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 69
![MCU 32BIT 64KB FLASH 32-QFN](/photos/28/61/286134/32-qfn_sml.jpg)
EFM32G200F64
Manufacturer Part Number
EFM32G200F64
Description
MCU 32BIT 64KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Geckor
Datasheets
1.EFM32G200F16.pdf
(63 pages)
2.EFM32G200F16.pdf
(10 pages)
3.EFM32G200F16.pdf
(463 pages)
4.EFM32G200F16.pdf
(136 pages)
Specifications of EFM32G200F64
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32G200
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
3.6.2.5 Examples
3.6.3 SDIV and UDIV
3.6.3.1 Syntax
3.6.3.2 Operation
3.6.3.3 Restrictions
3.6.3.4 Condition flags
3.6.3.5 Examples
3.7 Saturating instructions
3.7.1 SSAT and USAT
3.7.1.1 Syntax
2011-02-04 - d0002_Rev1.00
Signed Divide and Unsigned Divide.
SDIV{cond} {Rd,} Rn, Rm
UDIV{cond} {Rd,} Rn, Rm
where:
cond is an optional condition code, see Section 3.3.7 (p. 43) .
Rd
Rn
Rm
SDIV performs a signed integer division of the value in Rn by the value in Rm.
UDIV performs an unsigned integer division of the value in Rn by the value in Rm.
For both instructions, if the value in Rn is not divisible by the value in Rm, the result is rounded towards
zero.
Do not use SP and do not use PC.
These instructions do not change the flags.
This section describes the saturating instructions, SSAT and USAT.
Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating.
op{cond} Rd, #n, Rm {, shift #s}
UMULL
SMLAL
SDIV
UDIV
is the destination register. If Rd is omitted, the destination register is Rn.
is the register holding the value to be divided.
is a register holding the divisor.
R0, R2, R4
R8, R8, R1
R0, R4, R5, R6
R4, R5, R3, R8
; Signed divide, R0 = R2/R4
; Unsigned divide, R8 = R8/R1
; Unsigned (R4,R0) = R5 x R6
; Signed (R5,R4) = (R5,R4) + R3 x R8
...the world's most energy friendly microcontrollers
69
www.energymicro.com