EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 84
![MCU 32BIT 64KB FLASH 32-QFN](/photos/28/61/286134/32-qfn_sml.jpg)
EFM32G200F64
Manufacturer Part Number
EFM32G200F64
Description
MCU 32BIT 64KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Geckor
Datasheets
1.EFM32G200F16.pdf
(63 pages)
2.EFM32G200F16.pdf
(10 pages)
3.EFM32G200F16.pdf
(463 pages)
4.EFM32G200F16.pdf
(136 pages)
Specifications of EFM32G200F64
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32G200
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
3.10.7.2 Operation
3.10.7.3 Restrictions
3.10.7.4 Condition flags
3.10.7.5 Examples
3.10.8 NOP
3.10.8.1 Syntax
3.10.8.2 Operation
3.10.8.3 Condition flags
3.10.8.4 Examples
2011-02-04 - d0002_Rev1.00
Rn
spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK,
The register access operation in MSR depends on the privilege level. Unprivileged software can only
access the APSR, see Table 2.4 (p. 9) . Privileged software can access all special registers.
In unprivileged software writes to unallocated or execution state bits in the PSR are ignored.
Note
See Section 3.10.6 (p. 83) .
Rn must not be SP and must not be PC.
This instruction updates the flags explicitly based on the value in Rn.
MSR
No Operation.
NOP{cond}
where:
cond is an optional condition code, see Section 3.3.7 (p. 43) .
NOP does nothing. NOP is not necessarily a time#consuming NOP. The processor might remove it from
the pipeline before it reaches the execution stage.
Use NOP for padding, for example to place the following instruction on a 64#bit boundary.
This instruction does not change the flags.
CONTROL, R1 ; Read R1 value and write it to the CONTROL register
When you write to BASEPRI_MAX, the instruction writes to BASEPRI only if either:
• Rn is non-zero and the current BASEPRI value is 0
• Rn is non-zero and less than the current BASEPRI value.
is the source register.
BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
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