EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 78
![MCU 32BIT 64KB FLASH 32-QFN](/photos/28/61/286134/32-qfn_sml.jpg)
EFM32G200F64
Manufacturer Part Number
EFM32G200F64
Description
MCU 32BIT 64KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Geckor
Datasheets
1.EFM32G200F16.pdf
(63 pages)
2.EFM32G200F16.pdf
(10 pages)
3.EFM32G200F16.pdf
(463 pages)
4.EFM32G200F16.pdf
(136 pages)
Specifications of EFM32G200F64
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32G200
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
3.9.4 TBB and TBH
3.9.4.1 Syntax
3.9.4.2 Operation
3.9.4.3 Restrictions
2011-02-04 - d0002_Rev1.00
Table Branch Byte and Table Branch Halfword.
TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]
where:
Rn is the register containing the address of the table of branch lengths.
Rm is the index register. This contains an index into the table. For halfword tables, LSL #1 doubles
These instructions cause a PC#relative forward branch using a table of single byte offsets for TBB, or
halfword offsets for TBH. Rn provides a pointer to the table, and Rm supplies an index into the table. For
TBB the branch offset is twice the unsigned value of the byte returned from the table. and for TBH the
branch offset is twice the unsigned value of the halfword returned from the table. The branch occurs to
the address at that offset from the address of the byte immediately after the TBB or TBH instruction.
The restrictions are:
• Rn must not be SP
ITTE
ANDNE
ADDSNE R2, R2, #1
MOVEQ
CMP
ITE
ADDGT
ADDLE
IT
ITTEE
MOVEQ
ADDEQ
ANDNE
BNE.W
IT
ADD
If Rn is PC, then the address of the table is the address of the byte immediately following the TBB
or TBH instruction.
the value in Rm to form the right offset into the table.
NE
R0, R0, R1
R2, R3
R0, #9
GT
R1, R0, #55
R1, R0, #48
GT
EQ
R0, R1
R2, R2, #10
R3, R3, #1
dloop
NE
R0, R0, R1
; Next 3 instructions are conditional
; ANDNE does not update condition flags
; ADDSNE updates condition flags
; Conditional move
; Convert R0 hex value (0 to 15) into ASCII
; ('0'-'9', 'A'-'F')
; Next 2 instructions are conditional
; Convert 0xA -> 'A'
; Convert 0x0 -> '0'
; IT block with only one conditional instruction
; Next 4 instructions are conditional
; Conditional move
; Conditional add
; Conditional AND
; Branch instruction can only be used in the last
; instruction of an IT block
; Next instruction is conditional
; Syntax error: no condition code used in IT block
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ADDGT
R1, R1, #1
; Inc