EFM32G890F64 Energy Micro, EFM32G890F64 Datasheet - Page 203
EFM32G890F64
Manufacturer Part Number
EFM32G890F64
Description
MCU 32BIT 64KB FLASH 112-BGA
Manufacturer
Energy Micro
Series
Geckor
Datasheets
1.EFM32-G890F128-SK.pdf
(70 pages)
2.EFM32-G890F128-SK.pdf
(10 pages)
3.EFM32G200F16.pdf
(463 pages)
4.EFM32G200F16.pdf
(136 pages)
Specifications of EFM32G890F64
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT
Number Of I /o
90
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LFBGA
Processor Series
EFM32G890
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
90
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EFM32-G890F128-SK PDF datasheet
- EFM32-G890F128-SK PDF datasheet #2
- EFM32G200F16 PDF datasheet #3
- EFM32G200F16 PDF datasheet #4
- Current page: 203 of 463
- Download datasheet (8Mb)
16.5.5 USARTn_STATUS - USART Status Register
16.5.6 USARTn_CLKDIV - Clock Control Register
31:9
8
7
6
5
4
3
2
1
0
Offset
0x010
Reset
Access
Name
Bit
Offset
0x014
Reset
Access
Name
2010-09-06 - d0001_Rev1.00
Reserved
RXFULL
Set when the RXFIFO is full. Cleared when the receive buffer is no longer full. When this bit is set, there is still room for one more
frame in the receive shift register.
RXDATAV
Set when data is available in the receive buffer. Cleared when the receive buffer is empty.
TXBL
Indicates the level of the transmit buffer. If TXBIL is cleared, TXBL is set whenever the transmit buffer is empty, and if TXBIL is set,
TXBL is set whenever the transmit buffer is half-full or empty.
TXC
Set when a transmission has completed and no more data is available in the transmit buffer. Cleared when data is written to the
transmit buffer.
TXTRI
Set when the transmitter is tristated, and cleared when transmitter output is enabled.
RXBLOCK
When set, the receiver discards incoming frames. An incoming frame will not be loaded into the receive buffer if this bit is set at the
instant the frame has been completely received.
MASTER
Set when the USART operates as a master. Set using the MASTEREN command and clear using the MASTERDIS command.
TXENS
Set when the transmitter is enabled.
RXENS
Set when the receiver is enabled.
Name
0
0
1
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
R
R
R
R
R
R
R
R
R
Access
...the world's most energy friendly microcontrollers
203
Bit Position
Bit Position
RX FIFO Full
RX Data Valid
TX Buffer Level
TX Complete
Transmitter Tristated
Block Incoming Data
SPI Master Mode
Transmitter Enable Status
Receiver Enable Status
Description
www.energymicro.com
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