EFM32G890F64 Energy Micro, EFM32G890F64 Datasheet - Page 267
EFM32G890F64
Manufacturer Part Number
EFM32G890F64
Description
MCU 32BIT 64KB FLASH 112-BGA
Manufacturer
Energy Micro
Series
Geckor
Datasheets
1.EFM32-G890F128-SK.pdf
(70 pages)
2.EFM32-G890F128-SK.pdf
(10 pages)
3.EFM32G200F16.pdf
(463 pages)
4.EFM32G200F16.pdf
(136 pages)
Specifications of EFM32G890F64
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT
Number Of I /o
90
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LFBGA
Processor Series
EFM32G890
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
90
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EFM32-G890F128-SK PDF datasheet
- EFM32-G890F128-SK PDF datasheet #2
- EFM32G200F16 PDF datasheet #3
- EFM32G200F16 PDF datasheet #4
- Current page: 267 of 463
- Download datasheet (8Mb)
19.5.12 TIMERn_CCx_CTRL - CC Channel Control Register
31:18
17:16
15:11
10
9
8
7:3
2
1
0
31:28
27:26
25:24
Bit
Offset
0x030
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
LOCATION
Decides the location of the CC and CDTI pins.
Reserved
CDTI2PEN
Enable/disable CC channel 2 complementary dead-time insertion output connection to pin.
CDTI1PEN
Enable/disable CC channel 1 complementary dead-time insertion output connection to pin.
CDTI0PEN
Enable/disable CC channel 0 complementary dead-time insertion output connection to pin.
Reserved
CC2PEN
Enable/disable CC channel 2 output/input connection to pin.
CC1PEN
Enable/disable CC channel 1 output/input connection to pin.
CC0PEN
Enable/disable CC Channel 0 output/input connection to pin.
Reserved
ICEVCTRL
These bits control when a Compare/Capture PRS output pulse, interrupt flag and DMA request is set.
ICEDGE
These bits control which edges the edge detector triggers on. The output is used for input capture and external clock input.
Name
Name
Value
0
1
2
3
Value
0
1
2
3
Mode
LOC0
LOC1
LOC2
LOC3
Mode
EVERYEDGE
EVERYSECONDEDGE
RISING
FALLING
0x0
0
0
0
0
0
0
0x0
0x0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
RW
RW
RW
Access
Access
Description
Location 0
Location 1
Location 2
Location 3
Description
PRS output pulse, interrupt flag and DMA request set on every capture
PRS output pulse, interrupt flag and DMA request set on every second capture
PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE
= BOTH)
PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE
= BOTH)
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267
Bit Position
I/O Location
CC Channel 2 Complementary Dead-Time Insertion Pin Enable
CC Channel 1 Complementary Dead-Time Insertion Pin Enable
CC Channel 0 Complementary Dead-Time Insertion Pin Enable
CC Channel 2 Pin Enable
CC Channel 1 Pin Enable
CC Channel 0 Pin Enable
Input Capture Event Control
Input Capture Edge Select
Description
Description
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