EFM32G890F64 Energy Micro, EFM32G890F64 Datasheet - Page 246
EFM32G890F64
Manufacturer Part Number
EFM32G890F64
Description
MCU 32BIT 64KB FLASH 112-BGA
Manufacturer
Energy Micro
Series
Geckor
Datasheets
1.EFM32-G890F128-SK.pdf
(70 pages)
2.EFM32-G890F128-SK.pdf
(10 pages)
3.EFM32G200F16.pdf
(463 pages)
4.EFM32G200F16.pdf
(136 pages)
Specifications of EFM32G890F64
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT
Number Of I /o
90
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LFBGA
Processor Series
EFM32G890
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
90
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EFM32-G890F128-SK PDF datasheet
- EFM32-G890F128-SK PDF datasheet #2
- EFM32G200F16 PDF datasheet #3
- EFM32G200F16 PDF datasheet #4
- Current page: 246 of 463
- Download datasheet (8Mb)
19.3.1.3.3 Underflow/Overflow from Neighboring Timer
19.3.1.4 One-Shot Mode
19.3.1.5 Top Value Buffer
19.3.1.6 Quadrature Decoder
2010-09-06 - d0001_Rev1.00
All Timers are linked together (see Figure 19.4 (p. 246) ), allowing timers to count on overflow/underflow
from the lower numbered neighbouring timers to form a 32-bit or 48-bit timer. Note that all timers must
be set to same count direction and less significant timer(s) can only be set to count up or down.
Figure 19.4. TIMER Connections
By default, the counter counts continuously until it is stopped. If the OSMEN bit is set in the
TIMERn_CTRL register, however, the counter is disabled by hardware on the first update event. Note
that when the counter is running with CC1 as clock source (0b01 in CLKSEL in TIMERn_CTRL) and
OSMEN is set, a CC1 capture event will not take place on the update event (CC1 rising edge) that stops
the Timer.
The TIMERn_TOP register can be altered either by writing it directly or by writing to the TIMER_TOPB
(buffer) register. When writing to the buffer register the TIMERn_TOPB register will be written to
TIMERn_TOP on the next update event. Buffering ensures that the TOP value is not set below the
actual count value. The TOPBV flag in TIMERn_STATUS indicates whether the TIMERn_TOPB register
contains data that have not yet been written to the TIMERn_TOP register (see Figure 19.5 (p. 246) .
Figure 19.5. TIMER TOP Value Update Functionality
Quadrature Decoding mode is used to track motion and determine both rotation direction and position.
The Quadrature Decoder uses two input channels that are 90 degrees out of phase (see Figure 19.6 (p.
247) ).
TIMER2
APB Write (TOPB)
APB Write (TOP)
Update event
Underflow
Overflow
Set
Clear
TIMER1
TOPBV
Load APB
Load TOPB
Load APB
Underflow
Overflow
TOPB
TOP
TIMER0
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