MCIMX513CJM6CR2 Freescale Semiconductor, MCIMX513CJM6CR2 Datasheet - Page 177
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MCIMX513CJM6CR2
Manufacturer Part Number
MCIMX513CJM6CR2
Description
IC MPU I.MX51 529MABGA
Manufacturer
Freescale Semiconductor
Series
i.MX51r
Datasheet
1.MCIMX512DJM8C.pdf
(200 pages)
Specifications of MCIMX513CJM6CR2
Core Processor
ARM Cortex-A8
Core Size
32-Bit
Speed
600MHz
Connectivity
1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
128
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.8 V ~ 1.15 V
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
529-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Freescale Semiconductor
Contact Name
DRAM_CAS
DRAM_CS0
DRAM_CS1
DRAM_D10
DRAM_D12
DRAM_D13
DRAM_D14
DRAM_D15
DRAM_D16
DRAM_D17
DRAM_D18
DRAM_A13
DRAM_A14
DRAM_D11
DRAM_D19
DRAM_D20
DRAM_D21
DRAM_D22
DRAM_D23
DRAM_D24
DRAM_D25
DRAM_D0
DRAM_D1
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_D2
Table 131. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Assignment
Contact
AA3
W4
W3
W2
M3
M4
M1
M5
U1
R3
R2
H1
T2
V5
Y2
Y1
V3
V4
Y4
Y3
T1
L5
L4
L3
L2
L1
K1
K3
K4
K5
J3
J4
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
Power Rail
I/O Buffer Type
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
Package Information and Contact Assignments
Direction after
Reset
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
1
Configuraton
after Reset
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
1
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