MCIMX513CJM6CR2 Freescale Semiconductor, MCIMX513CJM6CR2 Datasheet - Page 70
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MCIMX513CJM6CR2
Manufacturer Part Number
MCIMX513CJM6CR2
Description
IC MPU I.MX51 529MABGA
Manufacturer
Freescale Semiconductor
Series
i.MX51r
Datasheet
1.MCIMX512DJM8C.pdf
(200 pages)
Specifications of MCIMX513CJM6CR2
Core Processor
ARM Cortex-A8
Core Size
32-Bit
Speed
600MHz
Connectivity
1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
128
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.8 V ~ 1.15 V
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
529-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Electrical Characteristics
1
2
4.7
The following sections provide information on external peripheral interfaces.
70
DDR24
DDR25
DDR26
Test conditions are: Capacitance of 15 pF for DDR contacts. The recommended drive strength is Medium for SDCLK and High
for address and controls
SDCLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value
and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and
SDCLK_B.
ID
DQS (input)
SDCLK_B
DQ (input)
SDCLK
DQS - DQ Skew (defines the Data valid window in read cycles related to
DQS).
DQS DQ in HOLD time from DQS
DQS output access time from SDCLK posedge
External Peripheral Interfaces
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Figure 36. DDR2 SDRAM DQ versus DQS and SDCLK Read Cycle
DDR26
DDR24
Table 63. DDR2 SDRAM Read Cycle
Parameter
DATA
DATA
DDR25
DATA
DATA
DATA
1
Symbol
t
t
DQSCK
DQSQ
t
QH
DATA
SDCLK = 200 MHz
–0.5
Min
1.8
—
Freescale Semiconductor
DATA
Max
0.35
0.5
—
DATA
2
Unit
ns
ns
ns
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