HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet - Page 90

• Manufacturer Part Number: HFIXF1110CC.B3-998844
• Description: IC ETHERNET MAC 10PORT 552-CBGA
• Manufacturer: Cortina Systems Inc

Specifications of HFIXF1110CC.B3-998844

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-4.2
• Voltage - Supply: 1.8 V, 2.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1010

IXF1110 MAC
Datasheet
250210, Revision 11.0
13 April 2009
5.8
5.8.1
5.8.1.1
5.8.1.2
5.8.2
Cortina Systems
Clocks
The IXF1110 MAC has system interface reference clocks, SPI4-2 data path input and output
clocks, a JTAG input clock, a
the unique clock source requirements.
System Interface Reference Clocks
There are two system interface clocks required by the IXF1110 MAC:
CLK125
The system interface clock, which supplies the clock to the majority of the internal circuitry,
is the 125 MHz clock. The source of this clock must meet the following specifications:
CLK50
The other system interface clock supplies the clock source to the SPI4-2 receive circuitry.
The source of this clock must meet the following specifications:
SPI4-2 Receive and Transmit Data Path Clocks
The SPI4-2 data path clocks are compliant with the OIF 2000.88.4 Specification.
The IXF1110 MAC has the following requirements on the transmit data path:
The IXF1110 MAC meets the following specifications on the receive data path:
®
• 3.3 V LVTTL drive
• +/- 50 ppm
• Maximum duty cycle distortion 40/60
• 3.3 V LVTTL drive
• 1/8 frequency of the SPI4-2 data path clock (RDCLK_P/N)
• Maximum duty cycle distortion 45/55
• Maximum peak-to-peak jitter (low and high frequency) of 125 pS
• Range = 42 Mhz to 50 MHz
• 2.5 V LVDS drive
• Maximum duty cycle distortion 45/55
• Maximum peak-to-peak jitter (low and high frequency) of 125 pS
• Stable (frequency and level) when reset is removed or when sourced, whichever
• TSCLK frequency is one-quarter TDCLK frequency
• 2.5 V LVDS drive
• Maximum duty cycle distortion 45/55
• Maximum peak-to-peak jitter (low and high frequency) of 125 pS
• Stable when sourced
IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller
happens last
I
2
C
output clock, and an LED output clock.
Section 5.8
5.8 Clocks
Page 90
details