78Q8430-100IGT/F Maxim Integrated Products, 78Q8430-100IGT/F Datasheet - Page 6

• Manufacturer Part Number: 78Q8430-100IGT/F
• Description: IC LAN MEDIA ACCESS CTLR 100LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 78Q8430-100IGT/F

• Controller Type: Ethernet Controller, MAC/PHY
• Voltage - Supply: 3.3V
• Current - Supply: 230mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -

78Q8430 Data Sheet
DS_8430_001
Figures
Figure 1: 78Q8430 Block Diagram ................................................................................................................ 7
Figure 2: Set Top Box Diagram .................................................................................................................... 8
Figure 3: Network Cameras Diagram ........................................................................................................... 8
Figure 4: Typical FXO VoIP Application ........................................................................................................ 9
Figure 5: Device Block Diagram ................................................................................................................... 9
Figure 6: GBI Bus Block Diagram ............................................................................................................... 10
Figure 7: Pinout ........................................................................................................................................... 11
Figure 8: Host Interface Timing Diagram .................................................................................................... 22
Figure 9: Host Bus Output Timing Diagram ................................................................................................ 23
Figure 10: Host Bus Input Timing Diagram ................................................................................................. 23
Figure 11: Bus Clock Timing ....................................................................................................................... 24
Figure 12: Internal Digital Block Diagram ................................................................................................... 25
Figure 13: Internal PHY Block Diagram ...................................................................................................... 26
Figure 14: Classification Architecture ......................................................................................................... 33
Figure 15: System Bus Interface Schematic ............................................................................................... 84
Figure 16: Line Interface Schematic ........................................................................................................... 85
Figure 17: LQFP Drawing ........................................................................................................................... 86
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