SI3015-FS Silicon Laboratories Inc, SI3015-FS Datasheet - Page 28

• Manufacturer Part Number: SI3015-FS
• Description: SI2400 ISOMODEM LINE-SIDE
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3015-FS

• Data Format: V.90
• Interface: Serial
• Voltage - Supply: 3.3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Baud Rates: -

Si2400
Clock Generation Subsystem
The Si2400 contains an on-chip clock generator. Using
a single master clock input, the Si2400 can generate all
modem sample rates necessary to support V.22bis,
V.22/Bell212A, and V.21/Bell103 standards and a
9.6 kHz rate for audio playback. Either a 4.9152 MHz
clock on XTALI or a 4.9152 MHz crystal across XTALI
and XTALO form the master clock for the Si2400. This
clock source is sent to an internal phase-locked loop
(PLL) which generates all necessary internal system
clocks. The PLL has a settling time of ~1 ms. Data on
RXD should not be sent to the device prior to settling of
the PLL.
The CLKOUT pin outputs a 78.6432 MHz/(N + 1) clock
which may be used to clock a microcontroller or other
devices in the system. N may be programmed via
SE1[4:0] (CLKD) to any value from 1 to 31. N defaults to
7 on power-up. CLKOUT is disabled by setting N = 0.
SE1[7:6] (MCKR) allows the user to control the
microcontroller clock rate. On powerup, the Si2400
28
Register
S1E
S1F
S2A
S2F
S20
S21
S22
S23
S24
S25
S26
S27
S28
S30
S31
S34
S35
VTSOH
VTSOL
TSOD
VDDH
FCDH
Name
VDDL
VTSO
RSOL
ATTD
TSOL
SPTL
RATL
TASL
TATL
RSO
FCD
UNL
Transmit Answer Tone Length
Answer Tone to Transmit Delay
Unscrambled Ones Length—V.22
Transmit Scrambled Ones Delay—V.22
Transmit Scrambled Ones Length—V.22
V.22/22b Data Delay Low
V.22/22b Data Delay High
S1 Pattern Time Length V.22b
V.22b 1200 bps Scrambled Ones Length
V.22b 2400 bps Scrambled Ones Length Low
V.22b 2400 bps Scrambled Ones Length High
Receive Scrambled Ones V.22b Length
FSK Connection Delay Low
FSK Connection Delay High
Receive Answer Tone Length
Answer Tone Length (only used in S1E [TATL] = 0x00)
Receive V.22 Scrambled Ones Length
Table 16. Handshaking Control Registers
Function
Rev. 1.1
UART DTE rate is set to 2400 bps, given that the clock
input is 4.9152 MHz. The MCKR register conserves
power via slower clocking of the microcontroller for
specific applications where power conservation is
required. Table 17 shows the configurations for different
values of MCKR.
SE1[7:6]
(MCKR)
0 0
0 1
1 0
1 1
Table 17. MCKR Configurations
Clock (MHz)
9.8304 MHz
4.9152 MHz
2.4576 MHz
Controller
Reserved
(256) 5/3 msec
(256) 5/3 msec
(256) 5/3 msec
53.3 msec
53.3 msec
5/3 msec
5/3 msec
5/3 msec
5/3 msec
5/3 msec
5/3 msec
5/3 msec
5/3 msec
5/3 msec
5/3 msec
5/3 msec
Units
1 sec
All (default)
All except V.22bis,
PCM
Command only
Reserved
Modes
Default
0xCB
0x2D
0x5D
0xA2
0x3C
0x0C
0xD2
0x3C
0x3C
0x5A
0xA2
0x03
0x09
0x08
0x78
0x08
0x00