DS90UR905QSQ/NOPB National Semiconductor, DS90UR905QSQ/NOPB Datasheet - Page 34

• Manufacturer Part Number: DS90UR905QSQ/NOPB
• Description: IC SER/DESERIAL 24BIT 48LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DS90UR905QSQ/NOPB

• Function: Serializer
• Data Rate: 1.82Gbps
• Input Type: Parallel
• Output Type: Serial
• Number Of Inputs: 24
• Number Of Outputs: 1
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Optional Serial Bus Control
The Ser and Des may also be configured by the use of a serial
control bus that is I2C protocol compatible. By default, the I2C
reg_0x00'h is set to 00'h and all configuration is set by control/
strap pins. A write of 01'h to reg_0x00'h will enable/allow con-
figuration by registers; this will override the control/strap pins.
Multiple devices may share the serial control bus since mul-
tiple addresses are supported. See
The serial bus is comprised of three pins. The SCL is a Serial
Bus Clock Input. The SDA is the Serial Bus Data Input / Out-
put signal. Both SCL and SDA signals require an external pull
up resistor to V
sistor to V
adjusted for capacitive loading and data rate requirements.
The signals are either pulled High, or driven Low.
The third pin is the ID[X] pin. This pin sets one of four possible
device addresses. Two different connections are possible.
The pin may be pulled to V
kΩ resistor; or a 10 kΩ pull up resistor (to V
V
to set other three possible addresses may be used. See
12
to VSS.
The Serial Bus protocol is controlled by START, START-Re-
peated, and STOP phases. A START occurs when SCL
transitions Low while SDA is High. A STOP occurs when SDA
transition High while SCL is also HIGH. See
DDIO
for the Ser and
)) and a pull down resistor of the recommended value
FIGURE 30. Serial Control Bus Connection
FIGURE 31. START and STOP Conditions
DDIO
DDIO
may be used. The resistor value may be
Table 13
. For most applications a 4.7 k pull up re-
for the Des. Do not tie ID[x] directly
DD
(1.8V, NOT V
Figure
30.
Figure 31
DDIO
DD
)) with a 10
1.8V, NOT
30102041
Table
30102051
34
To communicate with a remote device, the host controller
(master) sends the slave address and listens for a response
from the slave. This response is referred to as an acknowl-
edge bit (ACK). If a slave on the bus is addressed correctly,
it Acknowledges (ACKs) the master by driving the SDA bus
low. If the address doesn't match a device's slave address, it
Not-acknowledges (NACKs) the master by letting SDA be
pulled High. ACKs also occur on the bus when data is being
transmitted. When the master is writing data, the slave ACKs
after every data byte is successfully received. When the mas-
ter is reading data, the master ACKs after every data byte is
received to let the slave know it wants to receive another data
byte. When the master wants to stop reading, it NACKs after
the last data byte and creates a stop condition on the bus. All
communication on the bus begins with either a Start condition
or a Repeated Start condition. All communication on the bus
ends with a Stop condition. A READ is shown in
and a WRITE is shown in
Note: During initial power-up, a delay of 10ms will be required
before the I2C will respond.
If the Serial Bus is not required, the three pins may be left
open (NC).
*Note: RID
this is not a valid address.
Resistor
Resistor
RID* kΩ
RID* kΩ
(5% tol)
(5% tol)
TABLE 13. ID[x] Resistor Value – DS90UR906Q Des
TABLE 12. ID[x] Resistor Value – DS90UR905Q Ser
Open
Open
0.47
0.47
2.7
8.2
2.7
8.2
≠
0 ohm, do not connect directly to VSS (GND),
7b' 110 1010 (h'6A)
7b' 110 1011 (h'6B)
7b' 110 1110 (h'6E)
7b' 110 1001 (h'69)
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
Address
Address
7'b
7'b
Figure
33.
8b' 1101 1100 (h'DC)
8b' 1101 0010 (h'D2)
8b' 1101 0100 (h'D4)
8b' 1101 0110 (h'D6)
8b' 1110 1100 (h'EC)
8b' 1110 0010 (h'E2)
8b' 1110 0100 (h'E4)
8b' 1110 0110 (h'E6)
0 appended
0 appended
Address
(WRITE)
Address
(WRITE)
8'b
8'b
Figure 32