PI7C21P100BNHE Pericom Semiconductor, PI7C21P100BNHE Datasheet
PI7C21P100BNHE
Specifications of PI7C21P100BNHE
Available stocks
Related parts for PI7C21P100BNHE
PI7C21P100BNHE Summary of contents
Page 1
PCI-X TO PCI-X BRIDGE INTERNET: HTTP://WWW.PERICOM.COM PI7C21P100B Revision 1.02 3545 NORTH FIRST STREET SAN JOSE, CA 95134 PH: 1-877-PERICOM (1-877-737-4266) FAX: 1-408-435-1100 ...
Page 2
... A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product ...
Page 3
REVISION HISTORY Date Revision Number 11/05/2004 1.00 06/10/2005 1.01 11/21/2005 1.02 2-PORT PCI-X TO PCI-X BRIDGE Description First Release of Data Sheet Corrected package outline drawing in section 11 Removed “Advance Information” from the title Page November ...
Page 4
This page intentionally left blank. 2-PORT PCI-X TO PCI-X BRIDGE Page November 2005 – Revision 1.02 PI7C21P100B ...
Page 5
TABLE OF CONTENTS 1 DESCRIPTION................................................................................................................................... 9 2 FEATURES ......................................................................................................................................... 9 3 SIGNAL DEFINITIONS.................................................................................................................. 10 3.1 SIGNAL TYPES ....................................................................................................................... 10 3.2 SIGNALS .................................................................................................................................. 10 3.2.1 PRIMARY BUS INTERFACE SIGNALS............................................................................... 10 3.2.2 PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION.......................................... 12 3.2.3 SECONDARY ...
Page 6
ORDERING RULES................................................................................................................. 33 6 CLOCKS............................................................................................................................................ 35 6.1 PRIMARY AND SECONDARY CLOCK INPUTS................................................................. 35 6.2 CLOCK JITTER........................................................................................................................ 35 6.3 MODE AND CLOCK FREQUENCY DETERMINATION .................................................... 36 6.3.1 PRIMARY BUS ..................................................................................................................... 36 6.3.2 SECONDARY BUS ............................................................................................................... 36 6.3.3 CLOCK STABILITY.............................................................................................................. 37 ...
Page 7
INTERRUPT PIN REGISTER – OFFSET 3Ch ................................................................ 49 8.1.33 BRIDGE CONTROL REGISTER – OFFSET 3Ch ........................................................... 50 8.1.34 PRIMARY DATA BUFFERING CONTROL REGISTER – OFFSET 40h........................ 51 8.1.35 SECONDARY DATA BUFFERING CONTROL REGISTER – OFFSET 40h.................. 52 8.1.36 MISCELLANEOUS ...
Page 8
LIST OF TABLES T 3-1 PIN LIST 304-PIN PBGA .......................................................................................................... 19 ABLE T 4-1 PCI AND PCI-X TRANSACTIONS.......................................................................................... 22 ABLE T 4-2 WRITE TRANSACTION FORWARDING............................................................................... 23 ABLE T 4-3 READ TRANSACTIN HANDLING ......................................................................................... 25 ABLE T 4-4 DEVICE NUMBER TO ...
Page 9
DESCRIPTION The PI7C21P100B is a 2-port PCI-X 2.0 Bridge designed to be compliant with the PCI-X Addendum to the Local Bus Specification Revision 1.0a. The PI7C21P100B is able to handle 64-bit data at a maximum bus frequency of 133MHz. ...
Page 10
SIGNAL DEFINITIONS 3.1 SIGNAL TYPES Signal Type STS 3.2 SIGNALS Signal names that end with “#” are active LOW. 3.2.1 PRIMARY BUS INTERFACE SIGNALS Name Pin # P_AD[31:0] J23, M21, M22, L21, ...
Page 11
Name Pin # P_IRDY# A16 P_TRDY# B15 P_DEVSEL# D21 P_STOP# C4 P_LOCK# C14 P_IDSEL B19 P_PERR# C8 P_SERR# B4 P_REQ# B21 P_GNT# C20 P_RST# E22 Page 2-PORT PCI-X TO PCI-X BRIDGE Type Description STS Primary IRDY (Active ...
Page 12
PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION Name Pin # P_AD[63:32] B11, D10, C10, A4, B10, C9, B9, A3, B8, B3, C7, B7, D6, B6, B5, C2, D2, F4, E3, F3, B1, F2, G3, H3, H2, E1, J3, G1, ...
Page 13
SECONDARY BUS INTERFACE SIGNALS Name Pin # S_AD[31:0] N22, N21, P22, P21, M23, P20, N23, R22, T23, R21, W23, T22, U22, U21, V22, V21, W21, V20, AA20, AB18, Y18, AA16, AB15, AC17, AA13, AA12, AC15, AB11, AC11, AC9, AB9, ...
Page 14
Name Pin # S_PERR# AB17 S_SERR# AB19 S_REQ[6:2]# AC3, AB5, AB3, W2, AA2 S_REQ[1]# AA23 S_GNT[6:2]# AC4, AB4, AC5, Y2, AB1 S_GNT[1]# AA19 S_RST# U23 3.2.4 SECONDARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION Name Pin # S_AD[63:32] AB8, AB7, AA7, ...
Page 15
Name Pin # S_CBE[7:4]# Y10, AB10, AA11, AC8 S_PAR64 AA10 S_REQ64# AB13 S_ACK64# AA8 3.2.5 CLOCK SIGNALS Name Pin # P_CLK E21 S_CLK AB23 2-PORT PCI-X TO PCI-X BRIDGE Type Description TS Secondary Upper 32-bit Command/Byte Enables: Multiplexed command field ...
Page 16
STRAPPING PINS AND MISCELLANEOUS SIGNALS Name Pin # S__ARB# T21 S_SEL100 V3 S_PCIXCAP R23 S_PCIXCAP_PU AA1 S_DRVR AC7 P_DRVR E2 S_CLK_STABLE W3 S_IDSEL AA22 2-PORT PCI-X TO PCI-X BRIDGE Type Description I Internal Arbiter Enable: This pin is used ...
Page 17
Y22 BAR_EN G2 IDSEL_ROUTE AC22 OPAQUE_EN AA18 P_CFG_BUSY C6 RESERVED D1 3.2.7 JTAG BOUNDARY SCAN AND TEST SIGNALS Name Pin # TCK F21 TMS D22 TDO B23 TDI C22 2-PORT PCI-X TO PCI-X BRIDGE I PCI-X Device Bus Width: ...
Page 18
Name Pin # TRST# C23 3.2.8 TEST SIGNALS Name Pin # T_DI1 Y21 T_DI2 AA4 T_MODECTL C1 T_RI W22 XCLK_OUT D3 T_RI W22 TEST_CE0 Y23 3.2.9 POWER AND GROUND SIGNALS Name Pin # P_VDDA A21 P_VSSA D16 S_VDDA AB21 2-PORT ...
Page 19
Name Pin # S_VSSA Y16 VDD D9, D11, D13, D15, J4, J20, L4, L20, N4, N20, R4, R20, Y9, Y11, Y13, Y15 VDD2 A8, A12, A22, C5, D5, D7, D17, D19, E4, E20, G4, G20, H23, M1, T1, U4, U20, ...
Page 20
BALL PIN NAME TYPE LOCATION C11 P_CBE[5]# TS C13 P_AD[1] TS C15 P_AD[3] TS C17 P_AD[9] TS C19 P_AD[10] TS C21 VSS P C23 TRST P_AD[47 VSS P D6 P_AD[51 VSS P D10 P_AD[62] ...
Page 21
BALL PIN NAME TYPE LOCATION T1 VDD2 P T3 S_AD[50] TS T20 VSS P T22 S_AD[20 S_AD[42 S_AD[52] TS U20 VDD2 P U22 S_AD[19 VSS P V3 S_SEL100 I V20 S_AD[14] TS V22 S_AD[17] ...
Page 22
PCI BUS OPERATION This Chapter offers information about PCI transactions, transaction forwarding across PI7C21P100B, and transaction termination. The PI7C21P100B has two 2KB buffers for read data buffering of upstream and downstream transactions. Also, PI7C21P100B has two 1KB buffers for ...
Page 23
WRITE TRANSACTIONS Write transactions are treated as posted write, delayed/split (PCI-X), or immediate write transactions. Table 4-2 shows the method of forwarding used for each type of write operation. Table 4-2 WRITE TRANSACTION FORWARDING Type of Transaction Memory Write ...
Page 24
PI7C21P100B will restart the follow-on transactions if the queue has new data. PI7C21P100B ends the transaction on the target bus when one of the following conditions is met: All posted write data has been delivered to the target. ...
Page 25
PI7C21P100B attempts to transfer the write data on the PCI-X interface as soon as the transaction ends or a 128-byte boundary is crossed. Writes greater than 128 bytes are possible only if more than one 128-byte sector fills up before ...
Page 26
Type of Transaction Type 1 Configuration Read 4.3.1 MEMORY READ TRANSACTIONS Memory data is transferred from the originating side of PI7C21P100B to the destination side using PCI memory read, memory read line, memory read multiple, PCI-X memory read DWORD, and ...
Page 27
PI7C21P100B translates the conventional PCI memory read line command to the memory read block PCI-X command. Bits [23:22] offset 40h and bits [7:6] offset 40h control the mode of prefetching for memory read line transactions in the prefetchable range on ...
Page 28
TYPE 0 CONFIGURATION READ The Type 0 configuration read command is accepted on either the primary or secondary interface. The command returns immediate data on the primary interface regardless of the interface mode. On the secondary interface the command ...
Page 29
PCI TO PCI The method used for transfers in PCI-to-PCI mode is user defined in the primary and secondary data buffering control registers. These registers have bits for memory read to prefetchable space, memory read line, and memory read ...
Page 30
To support hierarchical PCI bus systems, two types of configuration transactions are specified: Type 0 and Type 1. Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 ...
Page 31
PI7C21P100B performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary interface and is intended for a device attached directly to the secondary interface. PI7C21P100B must convert the configuration command to a ...
Page 32
TYPE 1 TO TYPE 1 FORWARDING Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCI-to-PCI bridges are used. When PI7C21P100B detects a Type 1 configuration transaction intended for a ...
Page 33
PCI-X mode. Special cycles received by PI7C21P100B as a target are ignored. 5 TRANSACTION ORDERING To maintain data coherency and consistency, PI7C21P100B complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.2 ...
Page 34
SUMMARY OF TRANSACTION ORDERING IN PCI MODE Table 5-1 Table 5-2 show the ordering relationships of all the transactions and refers by number to the ordering rules that follow. Page PI7C21P100B 2-PORT PCI-X TO PCI-X BRIDGE and ...
Page 35
Table 5-1 SUMMARY OF TRANSACTION ORDERING IN PCI MODE Pass Posted Write Delayed Read Request Delayed Write Request Delayed Read Completion Delayed Write Completion 1. If the relaxed ordering bit is set in PCI to PCI mode, or the enable ...
Page 36
MODE AND CLOCK FREQUENCY DETERMINATION 6.3.1 PRIMARY BUS PI7C21P100B does not have I/O pins for the M66EN or PCIXCAP signals on the primary bus. PI7C21P100B adjusts its internal configuration based on the initialization pattern it detects on P_DEVSEL#, P_STOP#, ...
Page 37
Table 6-1 PROGRAMMABLE PULL-UP CIRCUIT 6.3.3 CLOCK STABILITY To comply with PCI and PCI-X architecture specifications, the bus clock must be stable and running at the designated frequency for at least 100us after deassertion of the bus reset. S_CLK_STABLE is ...
Page 38
Table 6-2 DRIVER IMPEDANCE SELECTION Primary Bus Default Driver Mode Mode (P_DRVR=0) Conventional 20 ohm PCI PCI ohm PCI-X 100 20 ohm PCI-X 133 20 ohm 7 RESET The primary and secondary interface each have their own asynchronous ...
Page 39
During this time delay period, the secondary bus mode and frequency is determined through the programmable pull-up circuit. This process may include up to 80us for the capacitive load on S_PCIXCAP to be charged. By the ...
Page 40
BUS PARKING & BUS WIDTH DETERMINATION Bus parking refers to driving the AD[31:0], CBE[3:0], and PAR lines to a known value while the bus is idle. In general, the device implementing the bus arbiter is responsible for parking the ...
Page 41
OPTIONAL CONFIGURATION ACCESS FROM THE SECONDARY BUS PI7C21P100B accepts Type 0 configuration transactions when the following conditions are met during the address phase: S_CBE[3:0]# indicates a configuration read or configuration write transaction S_AD[1:0] are 00 S_IDSEL is asserted Applications ...
Page 42
CONFIGURATION REGISTERS PCI configuration defines a 64 DWORD space to define various attributes of PI7C21P100B. 8.1 CONFIGURATION REGISTER SPACE MAP Table 8-1 CONFIGURATION SPACE MAP 31 – 24 Device ID Primary Status BIST Secondary Latency Timer Secondary Status Memory ...
Page 43
SIGNAL TYPE DEFINITION SIGNAL TYPE RO RW RWC 8.1.2 VENDOR ID REGISTER – OFFSET 00h BIT FUNCTION 15:0 Vendor ID 8.1.3 DEVICE ID REGISTER – OFFSET 00h BIT FUNCTION 31:16 Device ID 8.1.4 COMMAND REGISTER – OFFSET 04h BIT ...
Page 44
BIT FUNCTION 2 Bus Master Enable 1 Memory Space Enable 0 I/O Space Enable 8.1.5 PRIMARY STATUS REGISTER – OFFSET 04h BIT FUNCTION 31 Detected Parity Error 30 Signaled System Error 29 Received Master Abort 28 Received Target Abort 27 ...
Page 45
REVISION ID REGISTER – OFFSET 08h BIT FUNCTION 7:0 Revision ID 8.1.7 CLASS CODE REGISTER – OFFSET 08h BIT FUNCTION 31:24 Class Code 23:16 Sub Class Code 15:8 Programming Interface 8.1.8 CACHE LINE SIZE REGISTER – OFFSET 0Ch BIT ...
Page 46
LOWER MEMORY BASE ADDRESS REGISTER – OFFSET 10h BIT FUNCTION 31:20 Memory Base Address 19:4 Reserved 3 Prefetchable Indicator 2:1 Decoder Width 0 Decoder Type 8.1.13 UPPER MEMORY BASE ADDRESS REGISTER – OFFSET 14h BIT FUNCTION 31:0 Upper Memory ...
Page 47
I/O BASE ADDRESS REGISTER – OFFSET 1Ch BIT FUNCTION 7:4 I/O Base Address 3:2 Reserved 1:0 32-bit I/O Addressing 8.1.19 I/O LIMIT REGISTER – OFFSET 1Ch BIT FUNCTION 15:12 I/O Limit Address 11:10 Reserved 9:8 32-bit I/O Addressing 8.1.20 ...
Page 48
BIT FUNCTION 22 Reserved 21 66MHz Capable 20:16 Reserved 8.1.21 MEMORY BASE REGISTER – OFFSET 20h BIT FUNCTION 15:4 Memory Base 3:0 Reserved 8.1.22 MEMORY LIMIT REGISTER – OFFSET 20h BIT FUNCTION 31:20 Memory Limit 19:16 Reserved 8.1.23 PREFETCHABLE MEMORY ...
Page 49
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch BIT FUNCTION 31:0 Prefetchable Limit Upper 32-bit 8.1.27 I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h BIT FUNCTION 15:0 I/O Base Upper 16-bit 8.1.28 I/O LIMIT UPPER 16-BIT REGISTER – OFFSET ...
Page 50
BRIDGE CONTROL REGISTER – OFFSET 3Ch BIT FUNCTION 31:28 RESERVED 27 Discard Timer P_SERR# Enable 26 Master Timeout Status 25 Secondary Master Timeout Status 24 Primary Master Timeout Status 23 Fast Back-to-Back 22 Secondary Interface Reset 21 Master Abort ...
Page 51
BIT FUNCTION 16 Parity Error Response Enable 8.1.34 PRIMARY DATA BUFFERING CONTROL REGISTER – OFFSET 40h BIT FUNCTION 15 RESERVED 14:12 Maximum Memory Read Byte Count 11 Enable Relaxed Ordering 10 Primary Special Delayed Read Mode Enable 9:8 Primary Read ...
Page 52
SECONDARY DATA BUFFERING CONTROL REGISTER – OFFSET 40h BIT FUNCTION 31 RESERVED 30.28 Maximum Memory Read Byte Count 27 Enable Relaxed Ordering 26 Secondary Special Delayed Read Mode Enable 25:24 Secondary Read Prefetch Mode 23:22 Secondary Read Line Prefetch ...
Page 53
MISCELLANEOUS CONTROL REGISTER – OFFSET 44h BIT FUNCTION 7:3 RESERVED 2 Primary Configuration Busy 1 Data Parity Error Recovery Enable 0 Parity Error Behavior 8.1.37 EXTENDED CHIP CONTROL REGISTER 1 – OFFSET 48h BIT FUNCTION 7 RESERVED 6 Bridge ...
Page 54
BIT FUNCTION 3 Upstream Memory Read Prefetching Dynamic Control 2 Downstream Memory Read Prefetching Dynamic Control 1:0 RESERVED 8.1.38 EXTENDED CHIP CONTROL REGISTER 2 – OFFSET 48h BIT FUNCTION 11:10 Minimum Free Space in Memory Data FIFO Control (Secondary) 9:8 ...
Page 55
BIT FUNCTION 1 Broken Master Timeout Enable 0 External Arbiter 8.1.40 ARBITER ENABLE REGISTER – OFFSET 54h BIT FUNCTION 7 RESERVED 6 Enable Arbiter 6 5 Enable Arbiter 5 4 Enable Arbiter 4 3 Enable Arbiter 3 2 Enable Arbiter ...
Page 56
BIT FUNCTION 4 Arbiter Priority 4 3 Arbiter Priority 3 2 Arbiter Priority 2 1 Arbiter Priority 1 0 Arbiter Priority 0 8.1.42 SERR# DISABLE REGISTER – OFFSET 5Ch BIT FUNCTION 7:5 RESERVED 4 PERR# on Posted Writes SERR# Disable ...
Page 57
BIT FUNCTION 0 Secondary Retry Count SERR# Disable 8.1.43 PRIMARY RETRY COUNTER REGISTER – OFFSET 60h BIT FUNCTION 31 2G Retry Count Control 30:25 RESERVED 24 16M Retry Count Control 23:17 RESERVED 16 64K Retry Count Control 15:9 RESERVED 8 ...
Page 58
The below settings are the only allowed values. Other settings are not valid and will result in smaller retry counts. When the counter expires, the bridge discards the requested transaction on the secondary bus and issues SERR# on the primary ...
Page 59
OPAQUE MEMORY ENABLE REGISTER – OFFSET 70h BIT FUNCTION 7:1 RESERVED 0 Opaque Memory Enable 8.1.48 OPAQUE MEMORY BASE REGISTER – OFFSET 74h BIT FUNCTION 15:4 Opaque Memory Base Address 3:0 Address Select 8.1.49 OPAQUE MEMORY LIMIT REGISTER – ...
Page 60
OPAQUE MEMORY LIMIT UPPER 32-BIT REGISTER – OFFSET 7Ch BIT FUNCTION 31:0 Opaque Memory Base Upper 32-bit Register 8.1.52 PCI-X CAPABILITY ID REGISTER – OFFSET 80h BIT FUNCTION 7:0 PCI-X Capability ID 8.1.53 NEXT CAPABILITY POINTER REGISTER – OFFSET ...
Page 61
BIT FUNCTION 19 Unexpected Split Completion 18 Split Completion Discarded 17 133MHz Capable 16 64-bit Device 8.1.55 PCI-X BRIDGE PRIMARY STATUS REGISTER – OFFSET 84h BIT FUNCTION 31:22 RESERVED 21 Split Request Delayed 20 Split Completion Overrun 19 Unexpected Split ...
Page 62
BIT FUNCTION 7:3 Device Number 2:0 Function Number 8.1.56 SECONDARY BUS UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h BIT FUNCTION 31:16 Split Transaction Commitment Limit 15:0 Split Transaction Capability 8.1.57 PRIMARY BUS DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch BIT ...
Page 63
BIT FUNCTION 15:0 Split Transaction Capability 8.1.58 POWER MANAGEMENT ID REGISTER – OFFSET 90h BIT FUNCTION 7:0 Power Management ID 8.1.59 NEXT CAPABILITIES POINTER REGISTER – OFFSET 90h BIT FUNCTION 15:8 Next Capabilities Pointer 8.1.60 POWER MANAGEMENT CAPABILITIES REGISTER – ...
Page 64
BIT FUNCTION 14:13 Data Scale 12:9 Data Select 8 PME Enable 7:2 RESERVED 1:0 Power State 8.1.62 PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER – OFFSET 94h BIT FUNCTION 31:24 Data Register 23 Bus Power / Clock Control 22 B2/B3 Support for ...
Page 65
BIT FUNCTION 22 Private Device Mask 6 21 Private Device Mask 5 20 Private Device Mask 4 19:18 RESERVED 17 Private Device Mask 1 16:0 RESERVED 8.1.64 MISCELLANEOUS CONTROL REGISTER 2 – OFFSET B8h BIT FUNCTION 15 Short Term Caching ...
Page 66
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support boundary scan in PI721P100 for board-level continuity test and diagnostics. The TAP pins assigned are TCK, TDI, ...
Page 67
BOUNDARY SCAN REGISTER The boundary scan register is a required set of serial-shiftable register cells, formed by connecting boundary scan cells placed at the device’s signal pins into a shift register path. The VDD, VSS, and JTAG pins are ...
Page 68
Boundary Scan Register Number Pin Name 32 P_AD[31] 33 P_AD[32] 34 P_AD[33] 35 P_AD[34] 36 P_AD[35] 37 P_AD[36] 38 P_AD[37] 39 P_AD[38] 40 P_AD[39] 41 P_AD[40] 42 P_AD[41] 43 P_AD[42] 44 P_AD[43] 45 P_AD[44] 46 P_AD[45] 47 P_AD[46] 48 P_AD[47] ...
Page 69
Boundary Scan Register Number Pin Name 83 P_CFG_BUSY 84 P_PERR 85 P_REQ64 86 P_REQ 87 P_RST 88 P_SERR 89 P_STOP 90 P_TRDY 91 S_ACK64 92 S_AD[0] 93 S_AD[1] 94 S_AD[2] 95 S_AD[3] 96 S_AD[4] 97 S_AD[5] 98 S_AD[6] 99 S_AD[7] ...
Page 70
Boundary Scan Register Number Pin Name 134 S_AD[42] 135 S_AD[43] 136 S_AD[44] 137 S_AD[45] 138 S_AD[46] 139 S_AD[47] 140 S_AD[48] 141 S_AD[49] 142 S_AD[50] 143 S_AD[51] 144 S_AD[52] 145 S_AD[53] 146 S_AD[54] 147 S_AD[55] 148 S_AD[56] 149 S_AD[57] 150 S_AD[58] ...
Page 71
Boundary Scan Register Number Pin Name 185 S_REQ[3] 186 S_REQ[4] 187 S_REQ[5] 188 S_REQ64 189 S_REQ[6] 190 S_RST 191 S_SEL100 192 S_SERR 193 S_STOP 194 S_TRDY 195 BAR_EN 196 RESERVED 197 XCLK_OUT 198 S_IDSEL 199 64BIT_DEV 200 IDSEL_ROUTE 201 OPAQUE_EN ...
Page 72
Boundary Scan Register Number Pin Name 236 - 237 - 238 - 239 - 240 - 241 - 242 - 243 - 244 - 245 - 246 - 247 - 248 - 249 - 250 - 251 - 252 - ...
Page 73
Boundary Scan Register Number Pin Name 287 - 288 - 289 - 290 - 291 - 292 - 293 - 294 - 295 - 296 - 297 - 298 - 299 - 300 - 301 - 302 - 303 - ...
Page 74
Boundary Scan Register Number Pin Name 338 - 339 - 340 - 341 - 342 - 343 - 344 - 345 - 346 - 347 - 348 - 349 - 350 - 351 - 352 - 353 - 354 - ...
Page 75
ELECTRICAL INFORMATION 10.1 MAXIMUM RATINGS Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those ...
Page 76
AC SPECIFICATIONS Figure 10-1 PCI SIGNAL TIMING MEASUREMENTS Table 10-1 AC TIMING SPECIFICATIONS PCI-X MODE Symbol Parameter Input setup time to CLK – bussed T su signals Input setup time to CLK – point-to- T su(ptp) point signals Input ...
Page 77
POWER CONSUMPTION Power dissipation for V DD Power dissipation for V DD2 *Running at 133MHz 2-PORT PCI-X TO PCI-X BRIDGE PARAMETER (2.5V) (3.3V) Page PI7C21P100B RATING UNITS min typ max 1.33 W 0.46 W November 2005 ...
Page 78
... MECHANICAL INFORMATION Figure 11-1 PACKAGE DIAGRAM 31 X 31mm 304-PIN CSBGA 12 ORDERING INFORMATION PART NUMBER PI7C21P100BNH PI7C21P100BNHE 2-PORT PCI-X TO PCI-X BRIDGE SPEED PIN – PACKAGE 133MHz 304-PINS – CSBGA 133MHz 304-PIN – PB-FREE & GREEN CSBGA Page PI7C21P100B TEMPERATURE 0°C TO 85°C 0° ...
Page 79
NOTES: Page PI7C21P100B 2-PORT PCI-X TO PCI-X BRIDGE November 2005 – Revision 1.02 ...