IES5507T Hendon Semiconductors, IES5507T Datasheet - Page 8

• Manufacturer Part Number: IES5507T
• Description: Buffers & Line Drivers Buffered 4-Chan Bus Switch
• Manufacturer: Hendon Semiconductors

Specifications of IES5507T

• Logic Family: IES5507
• Number Of Channels Per Chip: 4
• Supply Voltage (max): 7 V
• Supply Voltage (min): - 0.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Output Current: 30 mA
• Output Voltage: 110 mV, 80 mV
• Supply Current: 0.1 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10 APPLICATION INFORMATION
10.1
Figure 12 shows a typical data transfer through the
IES5507. The IES5507 has excellent application to
extending loads and expanding the address space of slave
devices. Rise times are determined simply by the side of
the buffer with the slowest RC time constant.
Figure 13 shows a typical application for the IES5507.
Each channel can support up to the maximum permissible
capacitance load, thus the maximum loading of the system
can be 5x that which could be achieved with out buffering.
The channel enable function can be used to interface
buses of different operating frequencies. When certain bus
sections are enabled the system frequency may be limited
by a bus section having a slave device specified only to
100 kHz. When that bus section is disabled, the slow slave
is isolated and the remaining bus can be run at 400 kHz.
The timing performance and current sinking capability will
allow the IES5507 to run in excess of the 1MHz maximum
limit of the I
at 100kHz.
Figure 14 shows the IES5507 used as a line driver. Four
such lines (only one shown) can be run from the same
device. The receiving end may then again be used as a 4
way bus switch, radiating out into another four lines.
2009 Mar 05, Revision 1.0
(clock)
(data)
SDA
SCL
Design Considerations
Sequence
Start
2
C fast mode plus, or to run a huge 4nF of load
S
Master side of IES5507
Slave side of IES5507
(master)
A0
Device asserting data line (master/slave)
(master)
A1
Fig.12 Typical communication sequence through the IES5507
Purpose of Bit (Address Bit 5)
(master)
A2
Note: Input to Output delay exagerated for clarity
(master)
A3
(master)
Buffered 4-Channel 2-Wire Bus Switch
A4
8
Using the address pins, this entire structure may be
repeated. Thus a total of eight IES5507 “line drivers” may
be connected to a single bus master (U1), allowing for 32
(8x4) long distance bus pairs to be driven from the one I
port.
Figure 15 shows an alternative solution. In this case, the
IES5507 is used to isolate a P82B715 I
The P82B715 provides a “10x impedance
transformation”
buffer. Using the IES5507 to isolate this device greatly
simplifies calculation of the pull-ups and increases the total
system loading capability in extender applications. Of
course, it is possible to connect a P82B715 to each of the
four channels, thus allowing a significant drive capability.
The IES5507 may also be driven in series. Figure 16
shows this configuration. In this scenario, each of the four
outputs of the first device (U2) has six more IES5507’s
connected to it. Each of those six devices has four outputs,
thus giving 4x7x4 = 112 outputs. If the RESET pin on U2
was also driven from the master, it would be possible to
reproduce this entire structure multiple times, giving a truly
massive address space capability. Such a configuration
may be applied to situations such as display drivers.
(1) P82B715 I2C bus extender datasheet, 2 December 2003,
(master)
Philips Electronics N.V.
A5
“Hand-Over” pulses upon change
of device asserting the data line
(master)
SDA direction
A6
(1)
but does not isolate either side of the
(master)
W\
(slave)
ACK
Product Specification
IES5507
2
C bus extender.
Sequence
Stop
P
2
C