AT25256B-SSHL-B Atmel, AT25256B-SSHL-B Datasheet - Page 10

• Manufacturer Part Number: AT25256B-SSHL-B
• Description: EEPROM 256Kbit; SPI Bus High Spd; Mode 0 & 3
• Manufacturer: Atmel

Specifications of AT25256B-SSHL-B

• Memory Size: 256Kbit
• Memory Configuration: 32768 X 8
• Interface Type: Serial, SPI
• Clock Frequency: 3MHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Density: 256Kb
• Organization: 32Kx8
• Access Time (max): 80ns
• Frequency (max): 5MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Package Type: SOIC
• Operating Temp Range: -40C to 85C
• Supply Current: 10mA
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note:
3. Timing Diagram (for SPI Mode 0 (0,0)
Figure 3-1.
10
SCK
SO
CS
SI
If the device is not write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when
CS is brought high. A new CS falling edge is required to re-initiate the serial communication.
AT25128B/256B [Preliminary]
V
V
V
V
V
V
V
V
OH
OL
IH
IH
IH
IL
IL
IL
t
CSS
Synchronous Data Timing
HI-Z
(D7 - D0) to be programmed (). Programming will start after the CS pin is brought high. (The
Low-to-High transition of the CS pin must occur during the SCK low time immediately after clock-
ing in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status Register
(RDSR) Instruction. If Bit 0 = 1, the Write cycle is still in progress. If Bit 0 = 0, the Write cycle has
ended. Only the Read Status Register instruction is enabled during the Write programming
cycle.
The AT25128B/256B is capable of a 64-byte Page Write operation. After each byte of data is
received, the six low order address bits are internally incremented by one; the high order bits of
the address will remain constant. If more than 64 bytes of data are transmitted, the address
counter will roll over and the previously written data will be overwritten. The AT25128B/256B is
automatically returned to the write disable state at the completion of a Write cycle.
Table 2-6.
t
SU
Don’t Care Bits
Address
VALID IN
Address Key
A
N
t
WH
t
H
t
WL
AT25128B
A
A
15
13
t
V
• A
• A
14
0
t
HO
AT25256B
A
t
CSH
14
A
• A
15
8593C–SEEPR–8/09
0
t
DIS
t
HI-Z
CS