ispPAC-POWR1014A-01TN48I Lattice, ispPAC-POWR1014A-01TN48I Datasheet - Page 43

• Manufacturer Part Number: ispPAC-POWR1014A-01TN48I
• Description: Supervisory Circuits ispPAC-POWR1014 w/ A DC I
• Manufacturer: Lattice
• Type: Power Supply Sequencer and Monitorr
• Series: ispPAC®r

Specifications of ispPAC-POWR1014A-01TN48I

• Internal Hysteresis: Yes
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Output Type: Open Collector / Drain
• Number Of Voltages Monitored: 10
• Monitored Voltage: Adj V
• Undervoltage Threshold: Adj
• Overvoltage Threshold: Adj
• Manual Reset: No
• Watchdog: No
• Power-up Reset Delay (typ): 500 ms
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 20 mA
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-48
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 20mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
I2C_Control_Register Structure
Figure 2-35 shows the functions of each of the 12-bit I2C_Control_Register bits.
Figure 2-35. I2C_Control_Register
I2C_Data_Register Packet Structure
The 72-bit I2C_Data_Register packet is divided into 9 bytes.
• Bytes 9-7 contain the VMON status
• Bytes 6-5 contain ADC result
• Byte 4 controls/reads ADC Mux and ADC Input Attenuator
• Byte 3 controls/reads input pins/ status
• Bytes 2-1 control/read output pins/status
VMON Status Registers
Byte 9, Byte 8 and Byte 7: Byte 9 is the most significant byte and is shifted out last, ending with bit 71, VMON1A.
These bytes consist of the status of VMONxA and VMONxB comparators corresponding to VMON1 through
VMON10 inputs. In the following tables, the number in the parenthesis indicates the bit position within the
I2C_Data_Register Packet. During the I2C_Data_Register write operation, the contents of these bytes are ignored
because the VMON status registers are read only.
Bit
0 – Read ADC_MUX (Register 0x09)
1 – Write ADC_MUX (Register 0x09)*
X1,X0
0
0
1
1
Y1,Y0
0
0
1
1
Z1,Z0
0 0 – Read GP_OUTPUT2 (Register 0x0F)*
0 1 – Read OUTPUT_STATUS1 (Register 0x04)*
1 0 – Write GP_OUTPUT2 (Register 0x0F)*
1 1 – Not Valid
*Equivalent I
0 – Read INPUT VALUE (Register 0x11)*
1 – Read INPUT STATUS (Register 0x06)*
0 – Write INPUT_VALUE (Register 0x11)*
1 – Not Valid
0 – Read GP_OUTPUT1 (Register 0x0E)*
1 – Read OUTPUT_STATUS0 (Register 0x03)*
0 – Write GP_OUTPUT1 (Register 0x0E)*
1 – Not Valid
11
0
2
C port addresses are shown in parentheses.
10
0
9
0
8
1
7
1
0/1
6
2-43
X1
5
X0
4
ispPAC-POWR1014/A Data Sheet
Y1
3
Y0
2
Z1
1
Z0
0