M4A5-192/96-10VNC Lattice, M4A5-192/96-10VNC Datasheet - Page 13
M4A5-192/96-10VNC
Manufacturer Part Number
M4A5-192/96-10VNC
Description
CPLD - Complex Programmable Logic Devices HI PERF E2CMOS PLD
Manufacturer
Lattice
Datasheet
1.M4A5-6432-10JNC.pdf
(62 pages)
Specifications of M4A5-192/96-10VNC
Number Of Macrocells
192
Number Of Product Terms Per Macro
20
Maximum Operating Frequency
100 MHz
Delay Time
5 ns
Number Of Programmable I/os
680
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-144
Mounting Style
SMD/SMT
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Package
144TQFP
Family Name
ispMACHÂ 4A
Device System Gates
7500
Number Of Macro Cells
192
Maximum Propagation Delay Time
10 ns
Number Of User I/os
96
Typical Operating Supply Voltage
5 V
Operating Temperature
0 to 70 °C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing
flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization.
It can be selected to control reset or preset.
Note that the reset/preset swapping selection feature effects power-up reset as well. The initialization
functionality of the flip-flops is illustrated in Table 9. The macrocell sends its data to the output switch
matrix and the input switch matrix. The output switch matrix can route this data to an output if so desired.
The input switch matrix can send the signal back to the central switch matrix as feedback.
Note:
1. Transparent latch is unaffected by AR, AP
Product Term
Individual
Reset
Power-Up
a. Reset
Reset
Figure 8. Asynchronous Mode Initialization Configurations
D/L/T
AR
0
0
1
1
AP
Table 9. Asynchronous Reset/Preset Operation
AR
Q
ispMACH 4A Family
17466G-014
AP
0
1
0
1
Product Term
CLK/LE
Individual
X
X
X
X
Preset
1
Power-Up
See Table 8
Preset
Q+
1
0
0
b. Preset
D/L/T
AP
AR
Q
17466G-015
13