LC4256ZC-75TN100C Lattice, LC4256ZC-75TN100C Datasheet - Page 27

• Manufacturer Part Number: LC4256ZC-75TN100C
• Description: CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
• Manufacturer: Lattice

Specifications of LC4256ZC-75TN100C

• Memory Type: EEPROM
• Number Of Macrocells: 256
• Number Of Product Terms Per Macro: 80
• Maximum Operating Frequency: 200 MHz
• Delay Time: 4.5 ns
• Number Of Programmable I/os: 48
• Operating Supply Voltage: 1.8 V
• Supply Current: 0.341 mA
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-100
• Mounting Style: SMD/SMT
• Supply Voltage (max): 1.9 V
• Supply Voltage (min): 1.7 V
• Package: 100TQFP
• Family Name: ispMACH® 4000Z
• Number Of Macro Cells: 256
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 64
• Number Of Logic Blocks/elements: 36
• Typical Operating Supply Voltage: 1.8 V
• Operating Temperature: 0 to 90 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispMACH 4000V/B/C Internal Timing Parameters
In/Out Delays
t
t
t
t
t
t
Routing/GLB Delays
t
t
t
t
t
t
Register/Latch Delays
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IN
GOE
GCLK_IN
BUF
EN
DIS
ROUTE
MCELL
INREG
FBK
PDb
PDi
S
S_PT
ST
ST_PT
H
HT
SIR
SIR_PT
HIR
HIR_PT
COi
CES
CEH
SL
SL_PT
HL
GOi
Parameter
Input Buffer Delay
Global OE Pin Delay
Global Clock Input Buffer Delay
Delay through Output Buffer
Output Enable Time
Output Disable Time
Delay through GRP
Macrocell Delay
Input Buffer to Macrocell Register
Delay
Internal Feedback Delay
5-PT Bypass Propagation Delay
Macrocell Propagation Delay
D-Register Setup Time
(Global Clock)
D-Register Setup Time
(Product Term Clock)
T-Register Setup Time
(Global Clock)
T-Register Setup Time
(Product Term Clock)
D-Register Hold Time
T-Register Hold Time
D-Input Register Setup Time
(Global Clock)
D-Input Register Setup Time
(Product Term Clock)
D-Input Register Hold Time
(Global Clock)
D-Input Register Hold Time
(Product Term Clock)
Register Clock to Output/Feedback
MUX Time
Clock Enable Setup Time
Clock Enable Hold Time
Latch Setup Time
(Global Clock)
Latch Setup Time (Product Term
Clock)
Latch Hold Time
Latch Gate to Output/Feedback
MUX Time
Description
Over Recommended Operating Conditions
0.92
1.42
1.12
1.42
0.88
0.88
0.82
1.45
0.88
0.88
2.25
1.88
0.92
1.42
1.17
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-2.5
0.60
2.04
0.78
0.85
0.96
0.96
0.61
0.45
0.11
0.00
0.44
0.64
0.52
0.33
27
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ispMACH 4000V/B/C/Z Family Data Sheet
1.12
1.32
1.32
1.32
0.68
0.68
1.37
1.45
0.63
0.63
2.25
1.88
1.12
1.32
1.17
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-2.7
0.31
0.52
0.33
0.60
2.54
1.28
0.85
0.96
0.96
0.81
0.55
0.00
0.44
0.64
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.02
1.32
1.22
1.32
0.98
0.98
1.27
1.45
0.73
0.73
2.25
1.88
1.02
1.32
1.17
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-3
0.70
3.04
1.28
0.85
0.96
0.96
1.01
0.55
0.31
0.00
0.44
0.64
0.52
0.33
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.92
1.32
1.12
1.32
1.08
1.08
1.27
1.45
0.73
0.73
2.25
1.88
0.92
1.32
1.17
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-3.5
0.70
3.54
1.28
0.85
0.96
0.96
1.01
0.65
0.31
0.00
0.94
0.94
0.52
0.33
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns