AGL030V5-VQG100 Actel, AGL030V5-VQG100 Datasheet - Page 113

FPGA - Field Programmable Gate Array 30K System Gates

AGL030V5-VQG100

Manufacturer Part Number
AGL030V5-VQG100
Description
FPGA - Field Programmable Gate Array 30K System Gates
Manufacturer
Actel
Datasheet

Specifications of AGL030V5-VQG100

Processor Series
AGL030
Core
IP Core
Maximum Operating Frequency
892.86 MHz
Number Of Programmable I/os
79
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
30 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Table 2-167 • Output DDR Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDROCLKQ
DDROSUD1
DDROSUD2
DDROHD1
DDROHD2
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROWCLR1
DDROCKMPWH
DDROCKMPWL
DDOMAX
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
1.2 V DC Core Voltage
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
Data_R Data Hold for Output DDR
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
J
= 70°C, Worst-Case VCC = 1.14 V
Description
R ev i si o n 1 8
Table 2-7 on page 2-7
IGLOO Low Power Flash FPGAs
for derating values.
1.60
1.09
1.16
0.00
0.00
1.99
0.00
0.24
0.19
0.31
0.28
TBD
Std.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 99

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