AGLP060V5-CSG289 Actel, AGLP060V5-CSG289 Datasheet - Page 56
AGLP060V5-CSG289
Manufacturer Part Number
AGLP060V5-CSG289
Description
FPGA - Field Programmable Gate Array 60K System Gates
Manufacturer
Actel
Datasheet
1.AGLP125V5-CSG289.pdf
(128 pages)
Specifications of AGLP060V5-CSG289
Processor Series
AGLP060
Core
IP Core
Number Of Macrocells
512
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
4
Data Ram Size
4608 bit
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
60 K
Package / Case
CSP-289
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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IGLOO PLUS DC and Switching Characteristics
Table 2-72 • Parameter Definition and Measuring Nodes
2- 42
Parameter Name
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
*
OCLKQ
OSUD
OHD
OPRE2Q
OREMPRE
ORECPRE
OECLKQ
OESUD
OEHD
OEPRE2Q
OEREMPRE
OERECPRE
ICLKQ
ISUD
IHD
IPRE2Q
IREMPRE
IRECPRE
See
Figure 2-12 on page 2-41
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
for more information.
Parameter Definition
R ev i sio n 1 1
Measuring Nodes
(from, to)*
H, DOUT
H, EOUT
L, DOUT
I, EOUT
C, A
C, A
D, E
D, A
F, H
L, H
L, H
J, H
A, E
D, A
F, H
J, H
I, H
I, H
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