AGLP060V5-CSG289 Actel, AGLP060V5-CSG289 Datasheet - Page 59
AGLP060V5-CSG289
Manufacturer Part Number
AGLP060V5-CSG289
Description
FPGA - Field Programmable Gate Array 60K System Gates
Manufacturer
Actel
Datasheet
1.AGLP125V5-CSG289.pdf
(128 pages)
Specifications of AGLP060V5-CSG289
Processor Series
AGLP060
Core
IP Core
Number Of Macrocells
512
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
4
Data Ram Size
4608 bit
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
60 K
Package / Case
CSP-289
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 2-14 • Input Register Timing Diagram
Table 2-74 • Input Data Register Propagation Delays
Preset
Out_1
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
Clear
ICLKQ
ISUD
IHD
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
Data
CLK
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Input Register
Timing Characteristics
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
1.5 V DC Core Voltage
50%
1
50%
50%
t
ISUD
0
t
ICLKQ
t
IHD
50%
50%
J
= 70°C, Worst-Case VCC = 1.425 V
50%
t
IWPRE
Description
t
IPRE2Q
50%
50%
R ev i si o n 1 1
t
IRECPRE
t
50%
ICLR2Q
50%
t
IWCLR
50%
50%
50%
Table 2-6 on page 2-6
t
IRECCLR
IGLOO PLUS Low Power Flash FPGAs
50%
t
ICKMPWH
t
IREMPRE
50%
for derating values.
50%
t
ICKMPWL
0.41
0.32
0.00
0.57
0.57
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
Std.
50%
t
50%
IREMCLR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 45
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