LFXP3C-4TN144C Lattice, LFXP3C-4TN144C Datasheet - Page 238
LFXP3C-4TN144C
Manufacturer Part Number
LFXP3C-4TN144C
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V -4 Spd
Manufacturer
Lattice
Specifications of LFXP3C-4TN144C
Number Of Programmable I/os
100
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Appendix A. Using IPexpress™ to Generate DDR Modules
The input and output DDR module can be generated using IPexpress. The I/O section under the Architecture mod-
ules provides two options to the user:
IPexpress generates only the modules that are implemented within the IOLOGIC. Any logic required in the FPGA
core to complete the memory interface must be implemented by the user.
Figure 10-18. IPexpress I/O Section
DDR Generic
DDR Generic will generate the output DDR (ODDRXB) primitives for a given bus width. The user has the option to
enable or disable tristate control to the output DDR registers. Figure 10-19 shows the DDR Generic views of IPex-
press.
1. DDR_GENERIC – The option allows generation of a Generic DDR interface, which in the case of Lat-
2. DDR_MEM – This option allows the user to generate a complete DDR memory interface. It will generate
ticeECP/EC and LatticeXP devices, is only the output side DDR. The input side for a Generic DDR inter-
face must be implemented using PFU registers. Appendix D provides the example code for the input side
generic DDR.
both the read and write side interface required to interface with the memory.
10-19
LatticeECP/EC and LatticeXP
DDR Usage Guide
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