LFXP3C-4TN144C Lattice, LFXP3C-4TN144C Datasheet - Page 268
LFXP3C-4TN144C
Manufacturer Part Number
LFXP3C-4TN144C
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V -4 Spd
Manufacturer
Lattice
Specifications of LFXP3C-4TN144C
Number Of Programmable I/os
100
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
Note on the Primary Clock
The CLKOP must be used as the feedback source to optimize the PLL performance.
Most designers use the PLL for the clock tree injection removal mode and the CLKOP should be assigned as the
primary clock. This is done automatically by the software unless the user specifies otherwise.
CLKOP can route to CLK0 and CLK1 only. CLKOS/CLKOK can route to all primary clocks (CLK0 to CLK3).
When CLK2 or CLK3 is used as a primary clock and there is only one clock input to the DCS, the DCS is assigned
as a buffer mode by the software. Please see the DCS section of this document for further information.
Clock Net Preferences
There are two clock nets, primary clock and secondary clock.
As illustrated in Figure 11-9, users can set each clock to the desired clock net in the Pre-map Preference Editor or
write in the Preference File as shown in the examples below.
Primary-Pure and Primary-DCS
Primary Clock Net can be assigned to either Primary-Pure (CLK0 and CLK1) or Primary-DCS (CLK2 and CLK3).
Syntax Example
Global Primary Clock and Quadrant Primary Clock
Global Primary Clock
If a primary clock is not assigned as a quadrant clock, the software assumes it is a Global Clock.
There are two Global Primary/Pure Clocks and two Global Primary/DCS Clocks available.
Quadrant Primary Clock
Any Primary Clock may be assigned to a Quadrant Clock. The Clock may be assigned to a single quadrant or to
two adjacent quadrants (not diagonally adjacent).
When the quadrant clock net is used, users must ensure that the registers each clock drives can be assigned in
that quadrant without any routing issues.
With the Quadrant Primary Clocking scheme, the maximum number of Primary Clocks is 16 as long as all the Pri-
mary Clock Sources are avaialble.
Syntax Example
USE PRIMARY DCS NET "bf_clk";
USE PRIMARY PURE NET "bf_clk" QUADRANT_TL;
11-12
sysCLOCK PLL Design and Usage Guide
LatticeECP/EC and LatticeXP
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