LFE2M35SE-5FN484C Lattice, LFE2M35SE-5FN484C Datasheet - Page 309
LFE2M35SE-5FN484C
Manufacturer Part Number
LFE2M35SE-5FN484C
Description
FPGA - Field Programmable Gate Array 34K LUTs S-Ser SERDE S Mem DSP 1.2V -5
Manufacturer
Lattice
Datasheet
1.LFE2M35SE-5FN484C.pdf
(389 pages)
Specifications of LFE2M35SE-5FN484C
Number Of Macrocells
34000
Maximum Operating Frequency
320 MHz
Number Of Programmable I/os
303
Data Ram Size
2151424
Delay Time
12 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M35SE-5FN484C
Manufacturer:
LATTICE
Quantity:
210
Company:
Part Number:
LFE2M35SE-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LFE2M35SE-5FN484C
Manufacturer:
LATTICE
Quantity:
20 000
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LFE2M100E/SE Logic Signal Connections: 900 fpBGA
Lattice Semiconductor
Ball Number
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
D2
D3
H7
G6
D1
G5
G4
G3
H5
H4
G2
G1
H3
H2
N8
M9
E3
E4
F5
E2
K7
K8
E1
F2
F1
K6
K5
J8
J5
J4
L9
L7
L8
L6
J3
-
Ball/Pad Function
GNDIO7
GNDIO7
GNDIO7
GNDIO7
GNDIO7
GNDIO7
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
PL18B
PL25A
PL25B
PL26A
PL26B
PL28A
PL28B
PL29A
PL29B
PL30A
PL30B
PL31A
PL31B
PL32A
PL32B
PL33A
PL33B
PL34A
PL9A
PL9B
-
LFE2M100E/SE
Bank
4-206
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
-
-
-
-
-
LUM0_SPLLC_FB_A/LDQ15
LUM0_SPLLT_FB_A/LDQ15
LUM0_SPLLC_IN_A/LDQ15
LUM0_SPLLT_IN_A/LDQ15
LatticeECP2/M Family Data Sheet
Dual Function
VREF2_7
VREF1_7
LDQS15
LDQS32
LDQ15
LDQ15
LDQ15
LDQ15
LDQ15
LDQ15
LDQ15
LDQ15
LDQ15
LDQ15
LDQ15
LDQ23
LDQ23
LDQ23
LDQ23
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
Pinout Information
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
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