LFE2M35SE-5FN484C Lattice, LFE2M35SE-5FN484C Datasheet - Page 32
LFE2M35SE-5FN484C
Manufacturer Part Number
LFE2M35SE-5FN484C
Description
FPGA - Field Programmable Gate Array 34K LUTs S-Ser SERDE S Mem DSP 1.2V -5
Manufacturer
Lattice
Datasheet
1.LFE2M35SE-5FN484C.pdf
(389 pages)
Specifications of LFE2M35SE-5FN484C
Number Of Macrocells
34000
Maximum Operating Frequency
320 MHz
Number Of Programmable I/os
303
Data Ram Size
2151424
Delay Time
12 ns
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
LatticeECP2/M DSP Performance
Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of
the LatticeECP2/M family.
Table 2-11. DSP Performance
For further information about the sysDSP block, please see the list of additional technical information at the end of
this data sheet.
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysI/O buffers as shown in Figure 2-28. The PIO Block
supplies the output data (DO) and the tri-state control signal (TO) to the sysI/O buffer and receives input from the
buffer. Table 2-12 provides the PIO signal list.
ECP2M100
ECP2M20
ECP2M35
ECP2M50
ECP2M70
ECP2-12
ECP2-20
ECP2-35
ECP2-50
ECP2-70
ECP2-6
Device
DSP Block
2-29
18
22
22
24
42
3
6
7
8
6
8
LatticeECP2/M Family Data Sheet
DSP Performance
GMAC
10.4
23.4
28.6
10.4
28.6
31.2
54.6
3.9
7.8
9.1
7.8
Architecture
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