LFE2M20SE-5FN256C Lattice, LFE2M20SE-5FN256C Datasheet - Page 211

• Manufacturer Part Number: LFE2M20SE-5FN256C
• Description: FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5
• Manufacturer: Lattice

Specifications of LFE2M20SE-5FN256C

• Number Of Macrocells: 19000
• Maximum Operating Frequency: 311 MHz
• Number Of Programmable I/os: 140
• Data Ram Size: 1246208
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LFE2-50E/SE and LFE2-70E/SE Logic Signal Connections: 672 fpBGA
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
***Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
Number
Ball
U11
U13
U14
U16
U17
V13
V14
V21
P24
M3
V6
N6
Function
Ball/Pad
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
Bank
-
-
-
-
-
-
-
-
-
-
-
-
LFE2-50E/SE
Dual Function
Differential
4-108
Function
Ball/Pad
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
NC
NC
LatticeECP2/M Family Data Sheet
Bank
-
-
-
-
-
-
-
-
-
-
-
-
LFE2-70E/SE
Dual Function
Pinout Information
Differential