LFE2M20SE-5FN256C Lattice, LFE2M20SE-5FN256C Datasheet - Page 28

• Manufacturer Part Number: LFE2M20SE-5FN256C
• Description: FPGA - Field Programmable Gate Array 19K LUTs 140 I/O S-Ser SERDES DSP -5
• Manufacturer: Lattice

Specifications of LFE2M20SE-5FN256C

• Number Of Macrocells: 19000
• Maximum Operating Frequency: 311 MHz
• Number Of Programmable I/os: 140
• Data Ram Size: 1246208
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
MULTADDSUB sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-25
shows the MULTADDSUB sysDSP element.
Figure 2-25. MULTADDSUB
Multiplicand A0
Multiplicand A1
Multiplier B0
Multiplier B1
Signed A
Signed B
Addn
Shift Register B Out
Shift Register B In
n
n
Register B
Register B
Input Data
Input Data
n
n
n
n
n
Register
Register
Register
Input
Input
Input
m
m
Input Data
Register A
Input Data
Register A
m
Shift Register A Out
m
m
Shift Register A In
m
m
Register
Pipeline
Pipeline
Register
Pipeline
Register
Pipe
Pipe
Pipe
Reg
Reg
Reg
m
n
m
n
2-25
To Add/Sub
To Add/Sub
To Add/Sub
Multiplier
Multiplier
Register
Pipeline
Pipeline
Register
x
x
(default)
(default)
m+n
m+n
LatticeECP2/M Family Data Sheet
Add/Sub
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
(default)
m+n+1
(default)
m+n+1
Architecture
Output