MAX7032ATJ+ Maxim Integrated Products, MAX7032ATJ+ Datasheet - Page 20
MAX7032ATJ+
Manufacturer Part Number
MAX7032ATJ+
Description
RF Transceiver IC TXRX ASK/FSK PROG MHz Crystal-Based, P
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX7032ATJ.pdf
(32 pages)
Specifications of MAX7032ATJ+
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
300 MHz to 450 MHz
Output Power
6.7 dBm
Operating Supply Voltage
2.7 V, 5 V
Maximum Operating Temperature
+ 125C
Mounting Style
SMD/SMT
Maximum Supply Current
12.5 mA
Minimum Operating Temperature
- 40 C
Modulation
ASK/OOK.FSK
Package / Case
TQFN-32 EP
Data Rate
33Kbps
Supply Voltage Range
2.1V To 3.6V, 4.5V To 5.5V
Logic Case Style
QFN
No. Of Pins
32
Operating Temperature Range
-40°C To +125°C
Filter Terminals
SMD
Rohs Compliant
Yes
Data Rate Max
66Kbps
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
DIO is selected as an output of the MAX7032 for the fol-
lowing CS cycle whenever a READ command is
received. The CPU must tri-state the DIO line on the
cycle of CS that follows a read command, so the
MAX7032 can drive the data output line. Figure 9
shows the diagram of the 3-wire interface. Note that the
user can choose to send either 16 cycles of SLCK or
just eight cycles as all the registers are 8-bits wide. The
Figure 8. Data Input Diagram
Figure 9. Read Command on a 3-Wire Serial Interface
20
SCLK
SCLK
SCLK
DIO
DIO
DIO
CS
CS
______________________________________________________________________________________
CS
COMMAND
COMMAND
1
1
READ
READ
0
0
A5
A5
COMMAND
A4
A4
C1
ADDRESS
A3
A3
ADDRESS
C0
A2
A2
A5
A1
A1
A0
A0
A4
0
0
ADDRESS
A3
0
0
A2
0
0
0
DATA
DATA
0
A1
0
0
A0
0
0
user must drive DIO low at the end of the read
sequence.
The MASTER RESET command (0x3) (see Table 2)
sends a reset signal to all the internal registers of the
MAX7032 just like a power-off and power-on sequence
would do. The reset signal remains active for as long as
CS is high after the command is sent.
D7
0
0
0
0
D6
R7
R7
D5
R6
R6
D4
DATA
R5
R5
8 BITS OF DATA
REGISTER DATA
REGISTER DATA
D3
R4
R4
16 BITS OF DATA
R3
R3
D2
R2
R2
D1
R1
R1
A3
D0
R0
R7
REGISTER
DATA
R0