MSC7116VF1000 Freescale Semiconductor, MSC7116VF1000 Datasheet - Page 59

• Manufacturer Part Number: MSC7116VF1000
• Description: DSP 16BIT W/DDR CTRLR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC711x StarCorer
• Type: Fixed Pointr

Specifications of MSC7116VF1000

• Interface: Host Interface, I²C, UART
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (8 kB)
• On-chip Ram: 400kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: *
• Package / Case: 400-MAPBGA
• Device Core Size: 16b
• Format: Fixed Point
• Clock Freq (max): 266MHz
• Mips: 266
• Device Input Clock Speed: 266MHz
• Ram Size: 192KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.2/2.5/3.3V
• Operating Supply Voltage (min): 1.14/2.38/3.14V
• Operating Supply Voltage (max): 1.26/2.63/3.47V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 400
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7
Table 36
Freescale Semiconductor
Revision
10
12
13
11
0
1
2
3
4
5
6
7
8
9
provides a revision history for this data sheet.
Revision History
Aug. 2004
Sep. 2004
Mar. 2005
Dec. 2005
Nov. 2006
May 2004
Jan. 2005
Oct. 2005
Apr. 2005
Apr. 2007
Aug 2007
Apr 2004
Jul. 2007
Apr 2008
Date
• Initial public release.
• Added ordering information and new package options.
• Updated clock parameter values.
• Updated DDR timing specifications.
• Updated I
• Updated Figures 1-2 and 1-2 to correct HDSP and DBREQ.
• Corrected EE0 port reference.
• Updated ball location for HDSP.
• Added signal HA3.
• Updated absolute maximum ratings, DDR DRAM capacitance specifications, clock parameters, reset
• Added note for timing reference for I
• Expanded GPIO timing information.
• Corrected pin T20 and K20 signal designation.
• Corrected signal names to GPAO15 and IRQ2.
• Expanded design guidelines in Chapter 4.
• Updated features list.
• Updated power specifications.
• Changed CLKIN frequency range.
• Added clock configuration information.
• Updated JTAG timings.
• Added recommended power supply ratings and updated equations to estimate power consumption.
• Updated core and total power consumption examples.
• Added information about the new mask set 1M88B. Affected all sections.
• Updated arrows in Host DMA Writing Timing figure.
• Updated boot overview in Section 4.4.3.
• Removed erroneous references to V
• Updated to new data sheet format. Reorganized and renumbered sections, figures, and tables.
• Removed all references to obsolete mask set 1L44X and corresponding specification values.
• Added a note to clarify the definition of TCK timing 700 in new Table 31.
• Reworked reset and boot sections.
• Expanded I
• Removed obsolete part numbers.
• The power-up and power-down sequences described in Section 3.2 starting on page 42 have been expanded
• Change the PLL filter resistor from 20 Ω to 2 Ω in Section 3.2.5.
timing, and TDM timing.
to five possible design scenarios/cases. These cases replace the previously recommended
power-up/power-down sequence recommendations. Section 3.2 has been clarified by adding subsection
headings.
2
C timing specifications.
2
Table 36. Document Revision History
C boot information and added SPI boot information.
MSC7116 Data Sheet, Rev. 13
CCSYN
2
C interface.
and V
Description
CCSYN1
.
Revision History
59