XC3S1400AN-4FGG484C Xilinx Inc, XC3S1400AN-4FGG484C Datasheet - Page 52
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XC3S1400AN-4FGG484C
Manufacturer Part Number
XC3S1400AN-4FGG484C
Description
IC FPGA SPARTAN-3AN 484FPGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Specifications of XC3S1400AN-4FGG484C
Number Of Logic Elements/cells
25344
Number Of Labs/clbs
2816
Total Ram Bits
589824
Number Of I /o
372
Number Of Gates
1400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1400AN-4FGG484C
Manufacturer:
FREESCALE
Quantity:
902
Chapter 5: Erase Commands
Page Erase
52
The Page Erase command erases any individual page in the ISF memory array, as shown in
Figure
Buffer to Page Program without Built-in Erase
To perform a Page Erase command, the FPGA application must perform the following
actions.
•
•
Table 5-1: Page Erase (0x81) Command
•
Notes:
1. The Page Erase command is supported in simulation.
MOSI
Pin
Drive CSB Low while CLK is High or on the rising edge of CLK.
On the falling edge of CLK, serially clock in the appropriate Page Erase command
code, 0x81, most-significant bit first, as shown in
Similarly, serially clock in a 24-bit page address.
♦
♦
5-2. Typically, the Page Erase command is used to prepare a page for a subsequent
Only the page address is required. Any byte address values are ignored.
The number of pages and the alignment of the page address within the 24-bit
address field varies by Spartan-3AN FPGA type, as shown in
Page Erase
MOSI
MISO
Command
CSB
CLK
Byte 1
0x81
A Page Erase command will not
erase a page within a sector that
is protected by Sector Protect or
Sector Lockdown
SPI_ACCESS
(0x81)
Default Addressing: See
Optional Power-of-2 Addressing: See
Table A-4, page 89
www.xilinx.com
High Address
Figure 5-1: Page Erase Command
Byte 2
Page Address
Spartan-3AN FPGA In-System Flash User Guide
command.
Table 5-3
Selected ISF page is erased. Other
pages are unaffected .
24-bit Address
Middle Address
READY/BUSY
Status Register
Byte 3
7
0 = Page Erase in progress
1 = Selected page now erased
Table
Flash Memory Array
6
T
5-1.
5
PE
UG333 (v2.1) January 15, 2009
Page address
= 32 to 35 ms
4
3
UG333_c5_01_022207
Table
2
Byte Address
Low Address
Don’t Care
Unused
1
Byte 4
5-2.
XX
0
R