XC3S1400AN-5FGG484C Xilinx Inc, XC3S1400AN-5FGG484C Datasheet - Page 97
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XC3S1400AN-5FGG484C
Manufacturer Part Number
XC3S1400AN-5FGG484C
Description
IC FPGA SPARTAN-3AN 484FPGA
Manufacturer
Xilinx Inc
Series
Spartan™-3ANr
Specifications of XC3S1400AN-5FGG484C
Number Of Logic Elements/cells
25344
Number Of Labs/clbs
2816
Total Ram Bits
589824
Number Of I /o
372
Number Of Gates
1400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 76: Spartan-3AN FGG400 Pinout (Cont’d)
User I/Os by Bank
Table 77
The AWAKE pin is counted as a dual-purpose I/O.
Table 77: User I/Os Per Bank for the XC3S400AN in the FGG400 Package
Footprint Migration Differences
The XC3S400AN is the only Spartan-3AN FPGA offered in the FGG400 package.
The XC3S400AN FPGA is pin compatible with the Spartan-3A XC3S400A FPGA in the FG(G)400 package, although the
Spartan-3A FPGA requires an external configuration source.
DS557 (v4.1) April 1, 2011
Product Specification
Top
Right
Bottom
Left
VCCAUX TMS
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Bank
Package
Edge
Total
indicates how the 311 available user-I/O pins are distributed between the four I/O banks on the FGG400 package.
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
I/O Bank
Pin Name
0
1
2
3
Maximum I/Os
311
77
79
76
79
FGG400
Ball
N20
M11
N10
A13
E16
K13
K11
J10
J12
L10
L12
H1
M9
E4
T5
Y8
K9
L8
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
JTAG
Type
155
I/O
50
21
35
49
www.xilinx.com
INPUT
12
12
16
46
6
All Possible I/O Pins by Type
Spartan-3AN FPGA Family: Pinout Descriptions
DUAL
30
21
52
1
0
VREF
26
6
8
6
6
CLK
32
8
8
8
8
97
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