PIC18F45K80-I/P Microchip Technology, PIC18F45K80-I/P Datasheet - Page 500
![MCU PIC 32KB FLASH 40DIP](/photos/19/0/190060/4243276_sml.jpg)
PIC18F45K80-I/P
Manufacturer Part Number
PIC18F45K80-I/P
Description
MCU PIC 32KB FLASH 40DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F45K80-I/P
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Number Of I /o
35
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
Ram Memory Size
4KB
Cpu Speed
16MIPS
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, USART
Processor Series
PIC18F45K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F45K80-I/PT
Manufacturer:
MICROCHIP
Quantity:
1 500
Company:
Part Number:
PIC18F45K80-I/PT
Manufacturer:
PIC
Quantity:
400
Company:
Part Number:
PIC18F45K80-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F45K80-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC18F66K80 FAMILY
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39977C-page 500
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
No
No
No
Q1
Q1
Q1
PC
PC
Bit Test File, Skip if Clear
BTFSC f, b {,a}
0 f 255
0 b 7
a [0,1]
skip if (f<b>) = 0
None
If bit ‘b’ in register ‘f’ is ‘ 0 ’, then the next
instruction is skipped. If bit ‘b’ is ‘ 0 ’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘ 0 ’, the Access Bank is selected. If
‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction set
is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1(2)
Note: 3 cycles if skip and followed
register ‘f’
HERE
FALSE
TRUE
operation
operation
operation
Read
1011
No
No
No
=
=
=
=
=
Q2
Q2
Q2
by a 2-word instruction.
address (HERE)
0 ;
address (TRUE)
1 ;
address (FALSE)
BTFSC
:
:
bbba
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
FLAG, 1, 0
for details.
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
Preliminary
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
No
No
No
Q1
Q1
Q1
PC
PC
Bit Test File, Skip if Set
BTFSS f, b {,a}
0 f 255
0 b < 7
a [0,1]
skip if (f<b>) = 1
None
If bit ‘b’ in register ‘f’ is ‘ 1 ’, then the next
instruction is skipped. If bit ‘b’ is ‘ 1 ’, then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
If ‘a’ is ‘ 0 ’, the Access Bank is selected. If
‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing mode
whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1(2)
Note:
register ‘f’
HERE
FALSE
TRUE
operation
operation
operation
Read
1010
No
No
No
=
=
=
=
=
Q2
Q2
Q2
2011 Microchip Technology Inc.
address (HERE)
0 ;
address (FALSE)
1 ;
address (TRUE)
3 cycles if skip and followed
by a 2-word instruction.
BTFSS
:
:
bbba
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
FLAG, 1, 0
for details.
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
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