STM8L101G2U6A STMicroelectronics, STM8L101G2U6A Datasheet - Page 60
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STM8L101G2U6A
Manufacturer Part Number
STM8L101G2U6A
Description
IC MCU 8BIT 4KB FLASH 28UFQFPN
Manufacturer
STMicroelectronics
Series
STM8L EnergyLiter
Datasheet
1.STM8L101-EVAL.pdf
(81 pages)
Specifications of STM8L101G2U6A
Featured Product
STM32 Cortex-M3 Companion Products
Core Processor
STM8
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Infrared, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-UFQFN
Processor Series
STM8L10x
Core
STM8
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
26
Number Of Timers
3
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWSTM8
Minimum Operating Temperature
- 40 C
Eeprom Size
-
Data Converters
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM8L101G2U6A
Manufacturer:
STMicroelectronics
Quantity:
10 000
Electrical parameters
Note:
60/81
Inter IC control interface (I2C)
Subject to general operating conditions for V
The STM8L I
protocol described in the following table with the restriction mentioned below:
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Table 32.
1. f
2. Data based on standard I
3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
For speeds around 200 kHz, achieved speed can have 5% tolerance
For other speed ranges, achieved speed can have 2% tolerance
The above variations depend on the accuracy of the external components used.
t
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
su(SDA)
t
t
su(STO)
t
t
t
su(STA)
h(SDA)
period of SCL signal.
undefined region of the falling edge of SCL ).
r(SDA)
r(SCL)
f(SDA)
h(STA)
f(SCL)
SCK
C
b
must be at least 8 MHz to achieve max fast I
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition setup
time
STOP condition setup time
STOP to START condition time
(bus free)
Capacitive load for each bus line
I2C characteristics
2
C interface meets the requirements of the Standard I
2
Parameter
C protocol requirement, not tested in production.
Doc ID 15275 Rev 11
2
C speed (400 kHz).
DD
, f
MASTER
Standard mode
Min
0
250
4.7
4.0
4.0
4.7
4.0
4.7
-
-
-
(3)
(2)
I2C
, and T
Max
1000
300
400
-
-
-
-
-
-
-
-
(2)
A
unless otherwise specified.
2
Fast mode I2C
Min
C communication
0
100
1.3
0.6
0.6
0.6
0.6
1.3
-
-
-
(4)
(2)
Max
900
STM8L101xx
300
300
400
-
-
-
-
-
-
-
(3)
(1)
(2)
Unit
pF
ns
s
s
s
s