STM32F100RCT6 STMicroelectronics, STM32F100RCT6 Datasheet - Page 79
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STM32F100RCT6
Manufacturer Part Number
STM32F100RCT6
Description
IC ARM CORTEX MCU 256KB 64LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32F100RCT6TR.pdf
(97 pages)
Specifications of STM32F100RCT6
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
24MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
51
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LFQFP
Core
ARM Cortex M3
For Use With
STM32100B-EVAL - EVAL BOARD FOR STM32F100VBT6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F100RCT6
Manufacturer:
STMicroelectronics
Quantity:
500
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Part Number:
STM32F100RCT6
Manufacturer:
STMicroelectronics
Quantity:
10 000
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Part Number:
STM32F100RCT6B
Manufacturer:
SIPEX
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Part Number:
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Manufacturer:
STMicroelectronics
Quantity:
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Part Number:
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Part Number:
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Manufacturer:
STMicroelectronics
Quantity:
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Part Number:
STM32F100RCT6C
Manufacturer:
ST
Quantity:
20 000
STM32F100xC, STM32F100xD, STM32F100xE
Figure 30. SPI timing diagram - slave mode and CPHA = 0
Figure 31. SPI timing diagram - slave mode and CPHA = 1
1. Measurement points are done at CMOS levels: 0.3V
OUT P UT
OUT P UT
NSS input
NSS input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
I NPUT
I NPUT
MISO
MISO
MOSI
MOSI
t a(SO)
t SU(NSS)
t a(SO)
t su(SI)
t w(SCKH)
t w(SCKL)
t w(SCKH)
t w(SCKL)
t su(SI)
t SU(NSS)
MS B O UT
t v(SO)
M SB IN
M SB IN
t h(SI)
MS B O UT
t c(SCK)
t v(SO)
Doc ID 15081 Rev 5
t h(SI)
DD
t c(SCK)
and 0.7V
BI T6 OUT
B I T1 IN
t h(SO)
DD
.
B I T1 IN
BI T6 OUT
t h(SO)
LSB IN
t r(SCK)
t f(SCK)
LSB OUT
t r(SCK)
t f(SCK)
t h(NSS)
LSB IN
Electrical characteristics
t h(NSS)
LSB OUT
t dis(SO)
t dis(SO)
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