MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 10

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Features
GMII, RGMII, TBI, and RTBI physical interfaces . The eTSECs include 2 Kbyte receive and 10 Kbyte
transmit FIFOs and DMA functions.
The MPC8533E eTSECs support programmable CRC generation and checking, RMON statistics, and
jumbo frames of up to 9.6 Kbytes. Frame headers and buffer descriptors (BDs) can be forced into the L2
cache to speed classification or other frame processing. They are designed to comply with IEEE Std.
802.3™, 802.3u™, 802.3x™, 802.3z™, 802.3ac™, 802.3ab™. The BDs are based on the MPC8260 and
MPC860T 10/100 Ethernet programming models. Each eTSEC provides hardware support for
accelerating TCP/IP packet transmission and reception. By default, TCP/IP acceleration is not enabled and
the eTSEC processes frames as pure Ethernet frames, emulating a PowerQUICC III TSEC and allowing
existing driver software to be re-used with minimal change. Key features of these controllers include:
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Flexible configuration for multiple PHY interface configurations. Note that to allow maximum
flexibility with respect to protocol voltages and software compatibility, the MPC8533E offers two
eTSECs numbered, eTSEC1 and eTSEC3. As such, there are no interdependencies between the
two eTSEC controllers. The respective base register offsets also correspond to eTSECs 1 and 3 as
offered in other PowerQUICC III devices such the MPC8548E.
Ethernet standard interface capability – TBI, GMII, or MII
Ethernet reduced interface capability – RTBI, RGMII, or RMII
8-bit FIFO interface capability
TCP/IP acceleration and QoS features:
— IP v4 and IP v6 header recognition on receive
— IP v4 header checksum verification and generation
— TCP and UDP checksum verification and generation
— Per-packet configurable acceleration
— Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS stacks,
— Transmission from up to eight physical queues
— Reception to up to eight physical queues
Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex): IEEE Std. 802.3
full-duplex flow control (automatic PAUSE frame generation or software-programmed PAUSE
frame generation and recognition)
IEEE Std. 802.1 virtual local area network (VLAN) tags and priority
VLAN insertion and deletion
— Per-frame VLAN control word or default VLAN for each eTSEC
— Extracted VLAN control word passed to software separately
Programmable Ethernet preamble insertion and extraction of up to 7 bytes
Wake-on-LAN™ functionality
MAC address recognition
Ability to force allocation of header information and buffer descriptors into L2 cache
and ESP/AH IP-security headers
MPC8533E Integrated Host Processor Product Brief, Rev. 0
Freescale Semiconductor